[Original]. Read the experiment by using serial ADC tlc133, in the version

ArticleDirectory

• Schematic diagram
• Sequence Chart
• Notes
• Source code
• References

Schematic diagram

Sequence Chart

Notes

Source code

Top-level files

Module tlc_549_test (input clock_50, // input rst_n, // output adc549_clk, output adc549_data, // output [] seg7_seg, // seven-segment digital tube segment foot output [] seg7_dig // seven-segment digital tube foot); wire [] ad_data; tlc549_driver tlc549_driver_inst (. clock_50 (clock_50 ),. rst_n (rst_n ),//. ad_enable (1 'b1 ),. ad_data (ad_data ),//. NCS (adc549_cs_n ),. sck (adc549_clk ),. SDO (adc549_data); seg7x8_drive U0 (. I _clk (clock_50 ),. I _rst_n (rst_n ),. I _turn_off (8'b1111 _ 1100), // extinguish bits [2 hexadecimal]. I _dp (8' b0000 _ 0000), // decimal point [2 hexadecimal]. I _data (ad_data), // to display data [hexadecimal]. o_seg (seg7_seg ),. o_dig (seg7_dig); endmodule
 

Digital driver http://www.cnblogs.com/yuphone/archive/2011/04/24/2026318.html

Tlc549 driver

Module tlc549_driver (input clock_50, input rst_n, // input ad_enable, output Reg [7:0] ad_data, // output Reg NCs, output Reg sck, input SDO ); function Integer log2 (input integer N); integer I; for (I = 0; 2 ** I <= N; I = I + 1) log2 = I + 1; endfunction /************************************** * generate the tick clock of 40ns ********************************** * ***/REG cnt_40ns; always @ (posedge clock_50) cnt_40ns <= cnt_40ns + 1 'b1; W Ire tick_40ns = (cnt_40ns = 1 'b1 )? 1: 0; /*************************************** generate the ad benchmark counter *********************************** Based on the tick clock ********************************* * ***/REG [log2 (700): 1] ad_ref_cnt; // [1, 0,700] Always @ (posedge clock_50, negedge rst_n) if (! Rst_n) ad_ref_cnt <= 0; else begin if (! Ad_enable) ad_ref_cnt <= 0; else begin if (tick_40ns) begin if (ad_ref_cnt <700) ad_ref_cnt <= ad_ref_cnt + 1 'b1; else ad_ref_cnt <= 0; end end /************************************ ******************************* * *****/REG samping_flag; // sample flag always @ (posedge clock_50, negedge rst_n) if (! Rst_n) Begin NCS <= 1; sck <= 0; samping_flag <= 0; end else begin if (tick_40ns) Begin case (ad_ref_cnt) // sampling period 80,102,124,146,168,190: sck <= 1; 92,114,136,158,180,202,: sck <= 0; default:; // do not operate the endcase (ad_ref_cnt) 0: NCS <= 1; 1: NCS <= 0; // transition period 202: NCS <= 1; default:; // default: do not operate the endcase case (ad_ref_cnt) 0: samping_flag <= 0; // sample phase 36: samping_flag <= 1; // phase 202: Samping_flag <= 0; default:; // do not operate the endcase end endwire samping_end = (ad_ref_cnt = 202) by default )? 1: 0; // sampling end mark /********************************** **************************** * ********/REG [] sample_data; always @ (posedge sck, negedge rst_n) if (! Rst_n) sample_data <= {8 {1 'b0 }}; else begin if (sck) begin if (samping_flag! = 0) Begin sample_data [7] <= sample_data []; sample_data [0] <= SDO; end endalways @ (posedge clock_50, negedge rst_n) if (! Rst_n) ad_data <= {8 {1 'b0 }}; else begin if (samping_end) ad_data <= sample_data; else ad_data <= ad_data; endendmodule

SignalTap hardware simulation

References

Http://focus.ti.com.cn/cn/lit/ds/symlink/tlc549.pdf