[Original tutorial of black gold] [What about FPGA-driver I] [Experiment 1] Water lamp Module

Experiment 1: Flow lamp Module

For developers, the earth-moving ceremony is undoubtedly the most important task. For this reason, the water lamp experiment is no longer suitable for the low-level modeling II. Let's start the experiment.

Figure 1.1 create a model for an experiment.

As shown in 1.1, the experiment named "led_funcmod" function module. If you ignore the environment signal (the clock signal and reset signal), this function module only has a set of output terminals, that is, four-digit led signals. Next let's take a look at the specific content:

Led_funcmod.v

1.    module led_funcmod

2.    (

3.         input CLOCK, RESET,

4.         output [3:0]LED

5.    );

The above content is the access statement.

6.         parameter T1S = 26‘d50_000_000; //1Hz

7.         parameter T100MS = 26‘d5_000_000; //10Hz

8.         parameter T10MS = 26‘d500_000; //100Hz

9.         parameter T1MS = 26‘d50_000; //1000Hz

10.         

The above content is a constant declaration. The values range from 1 second to 1 millisecond.

11.         reg [3:0]i;

12.         reg [25:0]C1;

13.         reg [3:0]D;

14.         reg [25:0]T;

15.         reg [3:0]isTag;

16.         

17.         always @ ( posedge CLOCK or negedge RESET )

18.             if( !RESET )

19.                  begin

20.                         i <= 4‘d0;

21.                         C1 <= 26‘d0;

22.                         D <= 4‘b0001;

23.                         T <= T1S;

24.                         isTag <= 4‘b0001;

25.                    end

26.              else

The above content is related to the Register declaration and reset operation. Register I is used to point to the step, register C1 is used to count, register D is used to save the result and drive output, register t is used to save the count, and istag is used to save the delay label.

27.                case( i )

28.                

29.                      0:

30.                      if( C1 == T -1) begin C1 <= 26‘d0; i <= i + 1‘b1; end

31.                      else begin C1 <= C1 + 1‘b1; D <= 4‘b0001; end

32.                      

33.                      1:

34.                      if( C1 == T -1) begin C1 <= 26‘d0; i <= i + 1‘b1; end

35.                      else begin C1 <= C1 + 1‘b1; D <= 4‘b0010; end

36.                      

37.                      2:

38.                      if( C1 == T -1) begin C1 <= 26‘d0; i <= i + 1‘b1; end

39.                      else begin C1 <= C1 + 1‘b1; D <= 4‘b0100; end

40.                      

41.                      3:

42.                      if( C1 == T -1) begin C1 <= 26‘d0; i <= i + 1‘b1; end

43.                      else begin C1 <= C1 + 1‘b1; D <= 4‘b1000; end

44.                      

45.                      4:

46.                      begin isTag <= { isTag[2:0], isTag[3] }; i <= i + 1‘b1; end

47.                      

48.                      5:

49.                      if( isTag[0] ) begin T <= T1S; i <= 4‘d0; end

50.                      else if( isTag[1] ) begin T <= T100MS; i <= 4‘d0; end

51.                      else if( isTag[2] ) begin T <= T10MS; i <= 4‘d0; end

52.                      else if( isTag[3] ) begin T <= T1MS; i <= 4‘d0; end 

53.                      

54.              endcase        

55.        

56.        assign LED = D;

57.            

58.    endmodule

The above content is the core operation and output driver declaration. Step 0 ~ 3. Initially, the stop time for each step is 1 second, and then step 0 ~ 3. sequential execution results will be generated. Step 4 is used to switch the mode. Step 5 loads different delayed content for the T register based on the istag content, for example, [0] delay 1 second, [1] delay 100, [2] The latency is 10, and [3] The latency is 1. The default mode is 0 (24th rows), with a delay of 1 second (23rd rows ).

What this experiment cares about is not the experimental results, but the low-level modeling II itself. If we compare the flow experiment in modeling, there is a significant gap between low-level modeling I and low-level modeling II. First, low-level modeling II does not see counters, timers, and other peripheral operations. Furthermore, low-level modeling II has a high degree of integration, for example, STEP 0 ~ 3:

1.           0:

2.          if( C1 == T -1) begin C1 <= 26‘d0; i <= i + 1‘b1; end

3.          else begin C1 <= C1 + 1‘b1; D <= 4‘b0001; end 

4.          1:

5.          if( C1 == T -1) begin C1 <= 26‘d0; i <= i + 1‘b1; end

6.          else begin C1 <= C1 + 1‘b1; D<= 4‘b0010; end          

7.          2:

8.          if( C1 ==T -1) begin C1 <= 26‘d0; i <= i + 1‘b1; end

9.          else begin C1 <= C1 + 1‘b1; D <= 4‘b0100; end          

10.          3:

11.          if( C1 == T -1) begin C1 <= 26‘d0; i <= i + 1‘b1; end

12.          else begin C1 <= C1 + 1‘b1; D <= 4‘b1000; end

Code 1.1:

The content is shown in code 1.1, STEP 0 ~ 3. Each step represents a complete small operation. For example, if STEP 0 is set to 4 'b0001 for a period of time, step 1 is set to 4 'b0010 for a period of time, and step 2 ~ 3. -1 also takes into account the step switching time. Assuming that the interval between the flow is 1 million, each step will be accurate and stay at 50000 clocks. In fact, STEP 0 can also be replaced with a more convenient method, as shown in Code 1.2:

1.        reg [3:0] D = 4’b0001;  

2.        ......

3.        0,1,2,3：

4.        if( C1 == T -1) begin D <= { D[2:0], D[3] }; C1 <= 26‘d0; i <= i + 1‘b1; end

5.        else begin C1 <= C1 + 1‘b1; end

Code 1.2:

Code 1.2 indicates that as long as register D prepares the initial value, for example, 4 'b0001, STEP 0 ~ 3 can share the same operation, which will greatly reduce the number of rows and save space. Curious people may be confused. Since Code 1.2 is easy to write, why should I choose code 1.1? The reason is simple. It is to clarify the module content, so that we can easily make up the timing. Although both of them are similar, as long as we look at them, we will find that Code 1.2 is easy to write, but the details are vague and the content is not intuitive.

Here, I need to emphasize! Low-level modeling II, although integrated techniques make operations more convenient, focuses more on presentation and clarity than integrated. The key to doing so is to take the initiative to get rid of unnecessary simulation. Therefore, if the reader wants to be a friend of low-level modeling II, the definition of the content should be prioritized before modeling, rather than the simplification of the content. If the content is concise and intuitive, this is of course the best result.

As for experiment 1, there is no need for simulation, because the content is straightforward enough to complement the sequence. Finally, the author also said that although Experiment 1 has no learning value, the information to be expressed in Experiment 1 is also very clear, that is, low-level modeling II focuses on clear and intuitive modeling techniques. In addition, lab 1 can also be used as a warm-up for learning.