Orthogonal demodulation of the algorithm

Verlog language Before the interview really passed ...

1. Unsigned---Signed

2. Quadrature demodulation--1. Multiply the Cos 2. Take sin.

3. Quadrature demodulation---low-pass filtering

Module demodulation (INPUT wire CLK,
Input Wire clk_enable,
Input Wire Reset_n,
Input wire[9:0] Din_data,
Output WIRE[9:0] Dout_data
);

//////////////////////////////////////////////////////////
Unsigned---Signed
Wire [9:0] sigdata;
Assign sigdata = Din_data-10 ' d512;

//////////////////////////////////////////////////////////
sig_i = signal * cos
Sig_q = signal * sin

REG[9:0] Value_cos;
REG[9:0] Value_sin;
REG[1:0] Value_num;
Always @ (Posedge CLK or Negedge reset_n)
Begin
if (!reset_n) begin
Value_num <= 0;
End ELSE begin
Value_num <= value_num + 2 ' d1;
End
End

Always @ (Posedge CLK or Negedge reset_n)
Begin
if (!reset_n) begin
Value_cos <= 1;
End ELSE begin
Case (Value_num)
00:value_cos <= 1;
01:value_cos <= 0;
10:value_cos <=-1;
11:value_cos <= 0;
Endcase
End
End

Always @ (Posedge CLK or Negedge reset_n)
Begin
if (!reset_n) begin
Value_sin <= 0;
End ELSE begin
Case (Value_num)
00:value_sin <= 0;
01:value_sin <= 1;
10:value_sin <= 0;
11:value_sin <=-1;
Endcase
End
End

Wire [9:0] sig_i;
Wire [9:0] sig_q;

Assign sig_i = Sigdata * VALUE_COS;
Assign sig_q = Sigdata * Value_sin;

Low-pass filtering of I-Q signals respectively



Wire [9:0] sig_out_i;
Wire [9:0] sig_out_q;


Lpf_filter Low1 (. clk),
. clk_enable (1),
. Reset (Reset_n),
. Filter_din (Sig_i),
. Filter_dout (Sig_out_i)
);

Lpf_filter low2 (. clk),
. clk_enable (1),
. Reset (Reset_n),
. Filter_din (Sig_q),
. Filter_dout (SIG_OUT_Q)
);

To find the square root of the sum of squares


Sqrt sq1 (. clk),
. clk_enable (1),
. Reset_n (Reset_n),
. sqrt_x (Sig_out_i),
. Sqrt_y (Sig_out_q),
. Out_data (Dout_data));

To smooth ... Don't seem to need

Endmodule

Wire [19:0] tmp_x;
Wire [19:0] tmp_y;

Assign tmp_x = sqrt_x[9]? ({sqrt_x[9],10 ' b11111_11111,sqrt_x[8:0]}):({sqrt_x[9],10 ' b00000_00000,sqrt_x[8:0]});
Assign tmp_y = sqrt_y[9]? ({sqrt_y[9],10 ' b11111_11111,sqrt_y[8:0]}):({sqrt_y[9],10 ' b00000_00000,sqrt_y[8:0]});

Module Lpf_filter (INPUT wire CLK,
Input Wire clk_enable,
Input wire Reset,

Input wire[31:0] Dintick,
Output WIRE[31:0] Outtick,

Input wire [9:0] Filter_din,
Output wire [9:0] filter_dout);

Wire [31:0] filter_in;
Wire [31:0] filter_out;

Assign filter_in = filter_din[9]? ({filter_din[9],22 ' b11_11111_11111_11111_11111,filter_din[8:0]}):({filter_din[9],22 ' d0,filter_din[8:0]});

Assign filter_dout = filter_out[31]? ({filter_out[31],filter_out[24:16]}):({filter_out[31],filter_out[24:16]});

////////////////////////////////////////////////////////////////
Module Architecture:filter
////////////////////////////////////////////////////////////////
Local Functions
Type definitions
Constants

Parameter coeff1 = "d530"; 0.008084538.0845306443242445E-003; Double
Parameter coeff2 = "d1418"; 0.021641172.1641173173083540E-002; Double
Parameter COEFF3 = -32 ' d210; -0.00320142-3.2014226698098332e-003; Double
Parameter Coeff4 = -32 ' d677; -0.01032774-1.0327740008324267e-002; Double
Parameter Coeff5 = "d1386"; 0.02114663 2.1146841746630163E-002; Double
Parameter Coeff6 = -32 ' d1453; -0.02217336-2.2173359666555145e-002; Double
Parameter COEFF7 = + ' d427;//0.00651070 6.5107025473657917E-003; Double
Parameter Coeff8 = 2.4671686418581144E-002 ' d1617;//0.0246716864; Double
Parameter coeff9 = -32 ' d3849;//-0.05873706263-5.8373706263461472e-002; Double
Parameter COEFF10 = 7.1458229149308564E-002 ' d4683;//0.071458229149; Double
Parameter coeff11 = -32 ' d2339;//-0.035685782197-3.5685782197239432e-002; Double
Parameter coeff12 = -32 ' d5937;//-0.0905934127344-9.0593412734435275e-002; Double
Parameter coeff13 = 5.9152945051788575E-001 ' d38766;//0.591529450517; Double
Parameter Coeff14 = 5.9152945051788575E-001 ' d38766;//0.591529450517; Double
Parameter Coeff15 = -32 ' d5937;//-0.090593412733-9.0593412734435275e-002; Double
Parameter coeff16 = -32 ' d2339;//-0.035685782197-3.5685782197239432e-002; Double
Parameter coeff17 = 7.1458229149308564E-002 ' d4683;//0.0714582291493; Double
Parameter coeff18 = -32 ' d3849;//-0.05873706263-5.8373706263461472e-002; Double
Parameter coeff19 = 2.4671686418581144E-002 ' d1617;//0.02467168641858; Double
Parameter Coeff20 = 6.5107025473657917E-003 ' d427;//0.006510702547; Double
Parameter COEFF21 = -32 ' d1453;//-0.022173359666-2.2173359666555145e-002; Double
Parameter coeff22 = 2.1146841746630163E-002 ' d1386;//0.0211468417466; Double
Parameter coeff23 = -32 ' d677;//-0.01032774-1.0327740008324267e-002; Double
Parameter Coeff24 = -32 ' d210;//-0.0032014226698-3.2014226698098332e-003; Double
Parameter coeff25 = 2.1641173173083540E-002 ' d1418;//0.021641173173; Double
Parameter coeff26 = 8.0845306443242445E-003 ' d530;//0.0080084530644; Double

Signals
REG[31:0] delay_pipeline [0:25]; Double
REG[31:0] Product26; Double
REG[31:0] Product25; Double
REG[31:0] Product24; Double
REG[31:0] product23; Double
REG[31:0] product22; Double
REG[31:0] product21; Double
REG[31:0] product20; Double
REG[31:0] product19; Double
REG[31:0] product18; Double
REG[31:0] product17; Double
REG[31:0] product16; Double
REG[31:0] product15; Double
REG[31:0] product14; Double
REG[31:0] product13; Double
REG[31:0] product12; Double
REG[31:0] product11; Double
REG[31:0] product10; Double
REG[31:0] PRODUCT9; Double
REG[31:0] PRODUCT8; Double
REG[31:0] PRODUCT7; Double
REG[31:0] PRODUCT6; Double
REG[31:0] PRODUCT5; Double
REG[31:0] PRODUCT4; Double
REG[31:0] PRODUCT3; Double
REG[31:0] Product2; Double
REG[31:0] Product1_cast; Double
REG[31:0] Product1; Double
REG[31:0] SUM1; Double
REG[31:0] sum2; Double
REG[31:0] SUM3; Double
REG[31:0] SUM4; Double
REG[31:0] SUM5; Double
REG[31:0] SUM6; Double
REG[31:0] SUM7; Double
REG[31:0] SUM8; Double
REG[31:0] SUM9; Double
REG[31:0] SUM10; Double
REG[31:0] SUM11; Double
REG[31:0] SUM12; Double
REG[31:0] SUM13; Double
REG[31:0] SUM14; Double
REG[31:0] SUM15; Double
REG[31:0] SUM16; Double
REG[31:0] SUM17; Double
REG[31:0] SUM18; Double
REG[31:0] SUM19; Double
REG[31:0] SUM20; Double
REG[31:0] SUM21; Double
REG[31:0] SUM22; Double
REG[31:0] SUM23; Double
REG[31:0] Sum24; Double
REG[31:0] SUM25; Double
REG[31:0] Output_typeconvert; Double
REG[31:0] Output_register; Double

Block statements
Always @ (Posedge CLK or Posedge reset)
Begin:delay_pipeline_process
if (reset = = 1 ' B1) begin
Delay_pipeline[0] <= 0;
Delay_pipeline[1] <= 0;
DELAY_PIPELINE[2] <= 0;
DELAY_PIPELINE[3] <= 0;
DELAY_PIPELINE[4] <= 0;
DELAY_PIPELINE[5] <= 0;
DELAY_PIPELINE[6] <= 0;
DELAY_PIPELINE[7] <= 0;
Delay_pipeline[8] <= 0;
DELAY_PIPELINE[9] <= 0;
DELAY_PIPELINE[10] <= 0;
DELAY_PIPELINE[11] <= 0;
DELAY_PIPELINE[12] <= 0;
DELAY_PIPELINE[13] <= 0;
DELAY_PIPELINE[14] <= 0;
DELAY_PIPELINE[15] <= 0;
DELAY_PIPELINE[16] <= 0;
DELAY_PIPELINE[17] <= 0;
DELAY_PIPELINE[18] <= 0;
DELAY_PIPELINE[19] <= 0;
DELAY_PIPELINE[20] <= 0;
DELAY_PIPELINE[21] <= 0;
DELAY_PIPELINE[22] <= 0;
DELAY_PIPELINE[23] <= 0;
DELAY_PIPELINE[24] <= 0;
DELAY_PIPELINE[25] <= 0;
End
ELSE begin
if (clk_enable = = 1 ' B1) begin
Delay_pipeline[0] <= filter_in;
DELAY_PIPELINE[1] <= delay_pipeline[0];
DELAY_PIPELINE[2] <= delay_pipeline[1];
DELAY_PIPELINE[3] <= delay_pipeline[2];
DELAY_PIPELINE[4] <= delay_pipeline[3];
DELAY_PIPELINE[5] <= delay_pipeline[4];
DELAY_PIPELINE[6] <= delay_pipeline[5];
DELAY_PIPELINE[7] <= delay_pipeline[6];
DELAY_PIPELINE[8] <= delay_pipeline[7];
DELAY_PIPELINE[9] <= delay_pipeline[8];
DELAY_PIPELINE[10] <= delay_pipeline[9];
DELAY_PIPELINE[11] <= delay_pipeline[10];
DELAY_PIPELINE[12] <= delay_pipeline[11];
DELAY_PIPELINE[13] <= delay_pipeline[12];
DELAY_PIPELINE[14] <= delay_pipeline[13];
DELAY_PIPELINE[15] <= delay_pipeline[14];
DELAY_PIPELINE[16] <= delay_pipeline[15];
DELAY_PIPELINE[17] <= delay_pipeline[16];
DELAY_PIPELINE[18] <= delay_pipeline[17];
DELAY_PIPELINE[19] <= delay_pipeline[18];
DELAY_PIPELINE[20] <= delay_pipeline[19];
DELAY_PIPELINE[21] <= delay_pipeline[20];
DELAY_PIPELINE[22] <= delay_pipeline[21];
DELAY_PIPELINE[23] <= delay_pipeline[22];
DELAY_PIPELINE[24] <= delay_pipeline[23];
DELAY_PIPELINE[25] <= delay_pipeline[24];
End
End
End//delay_pipeline_process

Always @* product26 <= delay_pipeline[25] * COEFF26;

Always @* product25 <= delay_pipeline[24] * COEFF25;

Always @* product24 <= delay_pipeline[23] * COEFF24;

Always @* product23 <= delay_pipeline[22] * COEFF23;

Always @* product22 <= delay_pipeline[21] * COEFF22;

Always @* product21 <= delay_pipeline[20] * COEFF21;

Always @* product20 <= delay_pipeline[19] * COEFF20;

Always @* product19 <= delay_pipeline[18] * COEFF19;

Always @* product18 <= delay_pipeline[17] * COEFF18;

Always @* product17 <= delay_pipeline[16] * COEFF17;

Always @* product16 <= delay_pipeline[15] * COEFF16;

Always @* product15 <= delay_pipeline[14] * COEFF15;

Always @* product14 <= delay_pipeline[13] * COEFF14;

Always @* product13 <= delay_pipeline[12] * COEFF13;

Always @* product12 <= delay_pipeline[11] * COEFF12;

Always @* product11 <= delay_pipeline[10] * COEFF11;

Always @* product10 <= delay_pipeline[9] * COEFF10;

Always @* product9 <= delay_pipeline[8] * COEFF9;

Always @* product8 <= delay_pipeline[7] * COEFF8;

Always @* product7 <= delay_pipeline[6] * COEFF7;

Always @* product6 <= delay_pipeline[5] * COEFF6;

Always @* product5 <= delay_pipeline[4] * COEFF5;

Always @* product4 <= delay_pipeline[3] * COEFF4;

Always @* product3 <= delay_pipeline[2] * COEFF3;

Always @* product2 <= delay_pipeline[1] * COEFF2;

Always @* product1_cast <= product1;

Always @* product1 <= delay_pipeline[0] * COEFF1;

Always @* sum1 <= product1_cast + product2;

Always @* sum2 <= sum1 + product3;

Always @* sum3 <= sum2 + product4;

Always @* sum4 <= sum3 + product5;

Always @* sum5 <= sum4 + product6;

Always @* sum6 <= sum5 + product7;

Always @* sum7 <= sum6 + product8;

Always @* sum8 <= sum7 + product9;

Always @* sum9 <= sum8 + product10;

Always @* sum10 <= sum9 + product11;

Always @* sum11 <= SUM10 + product12;

Always @* sum12 <= Sum11 + product13;

Always @* sum13 <= sum12 + product14;

Always @* sum14 <= sum13 + product15;

Always @* sum15 <= sum14 + product16;

Always @* sum16 <= sum15 + product17;

Always @* sum17 <= sum16 + product18;

Always @* sum18 <= sum17 + product19;

Always @* sum19 <= sum18 + product20;

Always @* sum20 <= sum19 + product21;

Always @* sum21 <= sum20 + product22;

Always @* sum22 <= sum21 + product23;

Always @* sum23 <= sum22 + product24;

Always @* sum24 <= sum23 + product25;

Always @* sum25 <= Sum24 + product26;

Always @* output_typeconvert <= sum25;

Wire [31:0] tmp0;
Wire [31:0] TMP1;
Wire [31:0] TMP2;
Wire [31:0] Tmp3;
Wire [31:0] tmp4;
Wire [31:0] tmp;
Assign tmp0 = product1 + product2 + product3 + product4 + product5;
Assign TMP1 = product6 + product7 + product8 + product9 + product10;
Assign TMP2 = product11 + product12 + product13 + product14 + product15;
Assign Tmp3 = product16 + product17 + product18 + product19 + product20;
Assign Tmp4 = product21 + product22 + product23 + product24 + product25;
Assign TMP = tmp0 + tmp1 + tmp2 + Tmp3 + tmp4 + product26;
Assign Outtick = tmp;

Assign filter_out = tmp;
Assign filter_out = Output_typeconvert;

Endmodule

Module sqrt (input wire CLK,
Input Wire Reset_n,
Input Wire clk_enable,
Input wire [9:0] sqrt_x,
Input wire [9:0] sqrt_y,
Output wire [9:0] Out_data,
Output wire [19:0] Test0
);

The root of the sum of squares


Wire [19:0] tmp_x;
Wire [19:0] tmp_y;

Assign tmp_x = sqrt_x[9]? ({sqrt_x[9],10 ' b11111_11111,sqrt_x[8:0]}):({sqrt_x[9],10 ' b00000_00000,sqrt_x[8:0]});
Assign tmp_y = sqrt_y[9]? ({sqrt_y[9],10 ' b11111_11111,sqrt_y[8:0]}):({sqrt_y[9],10 ' b00000_00000,sqrt_y[8:0]});

Wire [19:0] tmp_data;

Assign tmp_data = tmp_x*tmp_x + tmp_y*tmp_y;

Assign test0 = Tmp_data;

REG[9:0] Reg_out_data;
Assign out_data = Reg_out_data;

REG[9:0] i=0;

Always @ (Posedge CLK or Negedge reset_n)
Begin
if (!reset_n) begin
Reg_out_data <= 0;
End ELSE begin
for (i=10 ' d0; i<10 ' d511; i=i+10 ' D1) begin
if (tmp_data >= i*i && tmp_data < (i+1) * (i+1)) begin
Reg_out_data <= i;
End
End

End
End

Endmodule

Orthogonal demodulation of the algorithm