Overview of AMBA, AHB, and APB bus

Introduction to AMBA, AHB, and APB bus)

 

 

About AMBA

With the development of deep sub-micron technology, the scale of Integrated Circuit chips is growing. From Time Series-driven design method to IP Reuse-based design method
It has been widely used. In the SOC design based on IP address multiplexing, on-chip bus design is the most critical issue. Therefore, many on-chip bus standards have emerged in the industry. Among them, the AMBA chip launched by arm
The bus has been favored by many IP developers and SoC system integrators and has become a popular industrial standard on-Chip structure. AMBA specifications mainly include the AHB (Advanced High Performance Bus) system bus and the APB (Advanced Peripheral Bus) peripheral bus.
 

AMBA On-Chip Bus


AMBA 2.0 consists of four parts: AHB, ASB, APB, and test methodology. AHB uses a traditional shared bus with the main module and the slave module.
Interfaces and interconnection functions are separated, which is of great significance for the interconnection between modules on the chip. AMBA is not only a bus, but also an interconnection system with interface modules.
Next we will briefly introduce the more important AHB and APB bus.

On-Chip System Based on AMBA

A typical AMBA-based system diagram 3 is shown.
Most modules (including processors) mounted on the bus are only functional modules with a single attribute: Main module or slave module. The main module is a module that sends read/write operations to the slave module, such as CPU and DSP. The slave module is a module that accepts commands and responds to the requests, such as on-chip RAM, AHB/APB bridge.
In addition, some modules have two attributes at the same time. For example, Direct Memory Access (DMA) is a slave module during programming, but it must be a master module when the system reads and transmits data.
For example
If there are multiple main modules on the bus, it is necessary to determine how to control the access of various main modules to the bus. Although the arbitration specification is part of the AMBA bus specification, the specific algorithm used is designed by RTL.
Engineers decided that two of the most common algorithms were fixed-priority and cyclic algorithms. A maximum of 16 master modules and any number of slave modules can be deployed on the AHB Bus. If the number of master modules is greater than 16
Add a layer of structure (For details, refer to the multi-layer AHB specification launched by arm ). The APB bridge is the only main module on the APB bus and the slave module on the AHB system bus.
Its main function is to lock the address, data, and control signals from the AHB system bus, and provide secondary decoding to generate the selection signal of APB peripheral devices, so as to realize the conversion from the AHB protocol to the APB protocol.

AHB Overview

AHB is mainly used for the connection between high-performance modules (such as CPU, DMA, and DSP). As an on-chip system bus of SOC, it includes the following features: single clock edge operation; non-triplicate implementers
Type; supports burst transmission; supports segmented transmission; supports multiple master controllers; supports 32-bit ~ 128-bit bus width; supports transmission of byte, half-byte, and word. AHB
The system consists of the main module, the slave module and the basic structure (infrastructure). The transmission of the entire AHB Bus is sent by the main module, and the slave module is responsible for responding. The basic structure is
Arbiter, main module to sub-module, multi-channel from module to main module, decoder, and Dummy
Slave) and dummy master. The interconnection structure 1 is shown in.

 

APB Overview

APB is mainly used for the connection between peripheral peripherals with low bandwidth, such as uart and 1284. Its bus architecture does not support multiple main modules like AHB. the only main module in APB is APB.
Bridge. Its features include: two clock-cycle transmission; no waiting period and response signal; simple control logic, only four control signals. The transmission on APB can be illustrated by the state chart 2.

1) The system is initialized to the idle status. At this time, no transmission operation is performed and no slave module is selected.

2) When there is a need for transmission, pselx = 1, penable = 0, the system enters the setup state, and will only stay in the setup State for one cycle. When the next rising edge of pclk arrives, the system enters the enable state.

3) when the system enters the enable state
Status of paddr, psel, pwrite unchanged, and set penable to 1. Transmission will only maintain a period in the enable State, after setup and enable
Status. If no data transmission is required, it enters the idle state and waits; if there is continuous data transmission, it enters the setup state.