Paging model
in x86, for example, Intel's processor's paging unit handles 4kB pages, and a 32-bit linear address (virtual address) is divided into 3 domains:-directory, directory, up to 10 bits -table, page table, Middle 10-bit -offset, offsets, 12-bit low- The address of the page directory being used is placed in the control register CR3, the directory field determines the catalog entry in the page directory, and table points to the appropriate page table entry that contains the physical address pointing to the page box.
Instead, offset determines the specific address within the page box.
-Address bit (31-12). The base address of the page Catalog item/Page table item/page. -P (0)-Existence bit (Present). Indicates that the page table or page directory is in, or is not in physical storage. 0 means no longer in main memory.
If the conversion to a virtual address is required for the page directory entry or the P-bit in the page table entry is 0, then the paging unit puts the virtual address into the control register CR2, and produces a fault. -R/W (1)--read/write Bit (read/write). Indicates whether the page is readable, writable, or read-only. However, r/w bit-to-page write protection only works when the processor is at the user privilege level.
When the processor is at the system privilege level, the R/W bit is ignored, which can always be read, written, or executed. -U/S (2)-User/Administrator bit (user/supervisor). Indicates that the page is available to the user layer (privilege Layer 3) and the administrator layer, and only to programs that can be used by the administrator layer (privileged layer 0~2). -PWT (3)--page Write bit (Page-level write Through). Controls cache write policies that use write-through or write-back. -PCD (4)--page cache disable bit (page-level cache Disable). Controls whether caching is prohibited or used. -A (5)--Access bit (accessed). When a page table or page is read or written, the processor will place the position. Once the processor is set, the bit no longer clears it, and only the software can reset it. -D (6)--dirty bit. Used only for page table entries, where the D-bit of a page table item is set when a write is made to the page involved. Similar access bits, only software can be reset. -PS (7)--only for page directory entries, if 1, indicates that the page catalog entry points to the 2MB/4MB page box. -Pat (7)--(Pentium III processor) Select a PAT (page Attribue table) item and select a Pat table entry along with the PCD PWT to select the memory type of the page. -G (8)--(Pentium Pro starts introducing) The 1 representation is a global page. You can prevent frequently used pages from being flushed out of the TLB. Only works if the page Global Entry (PGE) flag is set in CR4. -AVL (D9~D11)-the operating system private bit (Available for system's programmer use).
-The paging unit first compares the high 20 bits of the linear address to all 32 items in the TLB.
? If there is an address match (that is, a TLB hit), the base address of the page is directly obtained, and a 32-bit physical address is computed as long as the low 12-bit offset of the linear address is added.
? If there is no address match, the processor will perform a 2-level table-checking process. At the same time, the high 20-bit linear address read from the page table is stored in the TLB.
TLB
-The TLB (translation look-aside buffer) is actually a buffer that caches the page table entries in memory to speed up the conversion of virtual addresses to physical addresses.
If there is no TLB, then each fetch of data requires two visits (the page table gets the physical address + fetch data).
32-bit address division and cache
The Memory address is divided into 3 parts: tag, index, and block offset.
-Index corresponds to the cache row, tag corresponds to the highest bit of memory address, and block offset indicates the location of the required data in a cache row in data block. -The length of index =log2 (cache rows) -Block offset Length =log2 (bytes_per_data_block), 4K for page is 12
-The length of the tag =32–index–block offset -In the case of 32KB, 4-channel group, and the Cache with a row size of 16Bytes, the address is divided as follows when working properly: -The Cache is divided into rows, in line size, as a unit. Line is the Cache's data storage and management unit. A typical Cache row structure is:
-It consists of the Tag domain, the Status field, and the data field. -The Tag field holds the high of the corresponding address of the row data. After the CPU is indexed, the corresponding address is compared with the tag of all the rows in the group to differentiate the specific rows. -The number of bytes that the data field can hold is the row size (line size), which is the unit of data exchange between the Cache and memory. -The Status field is some control bit information (such as valid, Lock and parity check bit, etc.), different cache types, different cache implementation status field slightly different. -32*1024/(16 * 4) = 512 in the case of a 32KB 4-channel group and a cache with a row size of 16Bytes -When the CPU Access group is associated with the Cache, it is indexed to the group by index, and then the TAG is matched in the group for the road selection.
Page table, TLB, Cache Introduction (x86)
