Page table structure and page table entry format in x86

First, page table structure

The paging conversion feature is described by a table that resides in memory, called a page table, which is stored in the physical address space. The page table can be seen as a simple array of 220 physical addresses. The linear-to-physical address mapping function can simply be seen as an array lookup. The high 20 bits of the linear address form the index value of this array, which is used to select the physical (base) address of the corresponding page. The low 12 bits of the linear address give the offset in the page, plus the base address of the page eventually forms the corresponding physical addresses. Since the page base site is aligned on the 4K boundary, the low 12 bits of the page base address must be 0. This means that a high 20-bit page base address and a 12-bit offset connection are combined to get the corresponding physical address.

The size of each page table entry in the page table is 32 bits. Since only 20 bits are needed to hold the physical base address of the page, the remaining 12 bits can be used to hold property information such as whether the page exists or not. If the page table entry for a linear address index is labeled as present, then the item is valid and we can get the physical address of the page from it. If the information in the page table entry indicates that the page does not exist, an exception is generated when the corresponding physical page is accessed.

1. Level two page table structure

The page table contains a 1M table entry, each of which occupies 4 B. If stored as a table, they will consume up to 4MB of memory. Therefore, in order to reduce memory consumption, 80x86 uses a level two table. Thus, the conversion of the high 20-bit linear address to the physical address is also divided into two steps, each using (converting) one of the 10bit.

The first level table is called the page directory. It is stored on a 1-page 4K page with a table entry with a (1K) 4B length. These table entries point to the corresponding level two table. The highest 10 bits (bit 31~22) of a linear address are used as index values in the first table (page catalog) to select one of the 210 two-level tables.

The second-level table, called the page table, is also 1 pages long and contains up to 1K 4B of table entries. Each 4B table entry contains the 20-bit physical base address of the relevant page. The two-level page table uses the linear address middle 10 bit (bit 21~12) as the index value of the table item to get the table entry containing the page 20-bit physical base address. The 20-bit page is combined with a low 12-bit (in-page offset) of the physical base address and linear addresses to get the output value of the paging conversion process, which is the corresponding final physical address.

Figure 4-17 shows the lookup process for a level two table. Where the CR3 register specifies the base address of the page catalog table. The high 10 bits of the linear address are used to index this page table of contents to obtain pointers to related second-level page tables. The middle 10 bits of the linear address are used to index the two-level page table to obtain a high 20-bit physical address. The low 12 bits of the linear address are directly 12 bits lower than the physical address, thus forming a complete 32-bit physical address.

(Click to view larger image) Figure 4-17 transformation between a linear address and a physical address

2. Non-existent page table

Using a Level Two table structure does not solve the problem of having to use 4MB of memory to store page tables. In fact, we have made the problem a little bit more complicated. Because we need to add another page to store the table of contents. However, the Level two table structure allows page tables to be scattered across memory pages without needing to be stored in contiguous 4MB blocks of memory. In addition, there is no need to allocate a Level two page table for non-existent or linear address space unused portions. Although the Catalog table page must always exist in physical memory, the Level two page table can be redistributed when needed. This allows the size of the page table structure to correspond to the actual linear address space size used.

Each table item in the page catalog table also has an existing (present) property, similar to the table entry in the page table. The existence attribute in the page Catalog table entry indicates whether the corresponding Level two page table exists. If the Catalog table entry indicates that the corresponding Level two page table exists, then by accessing the level two table, the 2nd step of the table lookup process will continue as described above. If there is a bit indicating that the corresponding level two table does not exist, then the processor generates an exception to notify the operating system. The presence attribute in the Page Catalog table entry allows the operating system to allocate level two page table pages based on the range of linear addresses that are actually used.

The presence bit in the Catalog table entry can also be used to hold a Level two page table in virtual memory. This means that at any time only some of the two-level page tables need to be stored in physical memory, while the rest can be saved on disk. Page catalog entries that correspond to page tables in physical memory are labeled as present to indicate that they are available for paging conversions. Page catalog entries for page tables that are on disk will be labeled as nonexistent. The exception that is thrown because the two-level page table does not exist notifies the operating system to load the missing page table from the disk into physical memory. Storing the page table in virtual memory reduces the amount of physical storage that is required to save the paging conversion table.

Second, page table item format

The table entry format for page catalogs and page tables is shown in Figure 4-18. Where bit 31~12 contains a high 20-bit physical address that is used to locate the physical base site of a page (also called a page frame) in the physical address space. The low 12 bits of the table entry contain page property information. The previous article has discussed the existence of attributes, which briefly describe the functionality and purpose of the remaining properties.

(Click to view larger image) Figure 4-18 Page Table of Contents and page table item format

p--bit 0 is the presence (Present) flag that indicates whether the table entry is valid for address translation. P=1 is valid; p=0 means invalid. During page conversion, if the table entry for the page directory or page table involved is invalid, an exception is caused. If P=0, the rest of the bits are free for the program, as shown in Figure 4-18b, except that the table entry is invalid. For example, the operating system can use these bits to hold the ordinal of a page that has been stored on disk.

r/w--bit 1 is a read/write (read/write) flag. If it equals 1, the page can be read, written, or executed. If 0, indicates that the page is read-only or executable. The r/w bit does not work when the processor is running at the Super User privilege level (level 0, 1, or 2). The R/W bit in the page catalog item works for all pages that it maps.

u/s--bit 2 is the user/Super User (User/supervisor) flag. If it is 1, programs running at any privileged level can access the page. If 0, the page can only be accessed by programs running on the Super User privilege level (0, 1, or 2). The U/S bit in the page catalog item works for all pages that it maps.

a--bit 5 is the visited (accessed) flag. This Flag for page table entries is set to 1 when the processor accesses pages for page table entry mappings. When the processor accesses any page of the page Catalog table entry mapping, this flag of the page catalog table entry is set to 1. The processor is only responsible for setting the flag, and the operating system can count the usage of the page by periodically resetting the flag.

d--bit 6 is the page has been modified (DIRTY) flag. When the processor performs a write operation on a page, the D flag for the corresponding page table entry is set. The processor does not modify the D flag in the page catalog entry.

avl--the field is reserved for use by the program. The processor will not modify these, nor will the subsequent upgrade processors.