Paper:synthesizable finite state machine design techniques using the new SystemVerilog 3.0 enhancements's standard Verilog FSM conding Styles (two-segment)

1.TWO always block style with combinational outputs (good style)

The corresponding code is as follows:

2-Paragraph summary:

(1) The combinational always block sensitivity list was sensitve to changes on the state variable and all of the inputs Refe Renced in the combinaltional always block.

This is generally used [email protected] (*) on the OK.

(2) The combinaltional always block have a default next state assignments at the top of the "Always Block"

(3) Default output assignments is made prior to the case statement (this eliminates latches and reduces the amount of code Required to code the rest of the outputs in the case statement and Hightlights

In the case statement exactly in which states the individual output (s) change).

Start all output and next state variables to initialize the default values, otherwise there will be latches ( especially when the outputs is relatively long, it is easy to omit the individual output singals).

(4) in the states where the output assignment are not the default value assigned at the top of the block,the output Assig Nment is only made once for each state.

Each state, if output is not the default value, is only assigned once.

(5) The number of arcs (ARC) of the status jump is the same as the number of if-else-type statements.

(6) Each line has only one next_state statement, convenient reading debugging.

Default X-assignments Common trick:

Paper:synthesizable finite state machine design techniques using the new SystemVerilog 3.0 enhancements's standard Verilog FSM conding Styles (two-segment)