Part III: s5pv210_ Clock part _1

Clock part(1) clock domain

s5pv210 there are altogether three clock domains: Msys,dsys,psys

MSYS: (main system) master clock domain, including cpu,ddr memory, Irom and Iram, etc.

Dsys: (display system) shows the clock domain, which is generally related to video in this clock domain, such as hdmi,tvenc ...

PSYS: (peripheral system) Peripheral clock domain, is the Gpio interface, I²C interface, UART interface, and so on these peripheral devices on this clock domain.

Each clock domain is connected by a BRG (asynchronous bus Bridge).

(2) The source of the clock

Sources of common clocks:

　　External direct input clock signal, SOC has a pin used to input the external clock signal, with very little.

external crystal + internal clock generator clock generation, most of the low-frequency single-chip computer is the way to work.

　　　External crystal + Internal clock generator + internal PLL generates high frequency clock + inner part frequency divider to get clocks of various frequencies, 210 of which belongs to this.

Visible: Our 210 chip, generally from Xxti this interface into, this interface to connect the external crystal (specified is 24MHz), and then into the internal clock generator (Syscon), and then into 4 PLL, respectively, generated 4 different high-frequency clocks, Each high-frequency clock is then divided by the internal divider to get clocks of various frequencies.

Here is the range of frequencies that the various plls can produce:

(3) Typical values for each clock signal

Hclk_dsys:dsys high frequency line in clock domain;

Pclk_dsys:dsys the low frequency line of the clock domain;

(4) Each high-frequency clock through the internal divider division to get the clock value of various frequencies

(5) Code Analysis

There are five steps when setting up the clock:

1. Set a variety of clock switches, temporarily do not use the PLL

1 rreg_clk_src0 = 0x0; Its role: to let us temporarily do not use the PLL, only the original clock 24MHz

2. Set the lockout time, use the default value, set the PLL, the clock from the fin to the target frequency, it takes a certain amount of time, that is, lock time

1 rreg_apll_lock = 0x0000ffff;

2 rreg_mpll_lock = 0x0000ffff;

The default values are used:

3. Set the crossover

1 rreg_clk_div0 = 0x14131440;

4. Set up PPL

1     // FOUT = mdiv*fin/(pdiv*2^ (SDIV-1)) =0x7d*24/(0x3*2^ (1-1)) =1000 MHz 2     Rreg_apll_con0 = apll_val; 3     // FOUT = mdiv*fin/(pdiv*2^sdiv) =0x29b*24/(0xc*2^1) = 667 MHz 4     Rreg_mpll_con = Mpll_val;

The calculated data and formulas are already given, where m corresponds to the mdiv,p corresponding to the pdiv,s corresponding to the Sdiv

　The above corresponding to the APLL data and formula, we are set 1000MHz, so the value of M,p,s is: 125,3,1, bring into the formula can be

The following corresponds to the MPLL data and formulas, we are set 667MHz, so the value of M,p,s is: 667,12,1, bring into the formula can be

5. Set various clock switches, using the PLL

1 reg_clk_src0 = 0x10001111;

This completes the clock setup.

Finally, the complete code is attached:

1 //Clock controller Base address2 #defineElfin_clock_power_base 0xe01000003 4 //clock-dependent register relative to clock controller base address offset value5 #defineApll_lock_offset 0x006 #defineMpll_lock_offset 0x087 8 #defineApll_con0_offset 0x1009 #defineApll_con1_offset 0x104Ten #defineMpll_con_offset 0x108 One  A #defineClk_src0_offset 0x200 - #defineClk_src1_offset 0x204 - #defineClk_src2_offset 0x208 the #defineClk_src3_offset 0x20c - #defineClk_src4_offset 0x210 - #defineClk_src5_offset 0x214 - #defineClk_src6_offset 0x218 + #defineClk_src_mask0_offset 0x280 - #defineClk_src_mask1_offset 0x284 +  A #defineClk_div0_offset 0x300 at #defineClk_div1_offset 0x304 - #defineClk_div2_offset 0x308 - #defineClk_div3_offset 0x30c - #defineClk_div4_offset 0x310 - #defineClk_div5_offset 0x314 - #defineClk_div6_offset 0x318 in #defineClk_div7_offset 0x31c -  to #defineClk_div0_mask 0x7fffffff +  - //these configuration values for M, P, s are recommended for the typical clock configuration values in the data sheet.  the //These configuration values are recommended by Samsung and therefore work most reliably. If it's a piece of your own, it's going to be * //after rigorous testing, we can guarantee certain right.  $ #defineApll_mdiv 0x7d// thePanax Notoginseng #defineApll_pdiv 0x3 - #defineApll_sdiv 0x1 the  + #defineMpll_mdiv 0x29b//667 A #defineMpll_pdiv 0xc the #defineMpll_sdiv 0x1 +  - #defineSET_PLL (MDiv, Pdiv, Sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) $ #defineApll_val SET_PLL (Apll_mdiv,apll_pdiv,apll_sdiv) $ #defineMpll_val SET_PLL (Mpll_mdiv,mpll_pdiv,mpll_sdiv) -  -  the #defineREG_CLK_SRC0 (Elfin_clock_power_base + clk_src0_offset) - #defineReg_apll_lock (Elfin_clock_power_base + apll_lock_offset)Wuyi #defineReg_mpll_lock (Elfin_clock_power_base + mpll_lock_offset) the #defineReg_clk_div0 (Elfin_clock_power_base + clk_div0_offset) - #defineReg_apll_con0 (Elfin_clock_power_base + apll_con0_offset) Wu #defineReg_mpll_con (Elfin_clock_power_base + mpll_con_offset) -  About #defineRREG_CLK_SRC0 (* (volatile unsigned int *) REG_CLK_SRC0) $ #defineRreg_apll_lock (* (volatile unsigned int *) reg_apll_lock) - #defineRreg_mpll_lock (* (volatile unsigned int *) reg_mpll_lock) - #defineRreg_clk_div0 (* (volatile unsigned int *) reg_clk_div0) - #defineRreg_apll_con0 (* (volatile unsigned int *) reg_apll_con0) A #defineRreg_mpll_con (* (volatile unsigned int *) Reg_mpll_con) +  the  - voidClock_init (void) $ { the     //1 set a variety of clock switches, temporarily do not use the PLL theRREG_CLK_SRC0 =0x0; the      the     //2 Set the lock time, use the default value -     //when the PLL is set, the clock is lifted from fin to the target frequency, which takes a certain amount of time, i.e. lockout time inRreg_apll_lock =0x0000ffff; theRreg_mpll_lock =0x0000ffff; the      About     //3 Setting the crossover the     //Qing bit[0~31] theRreg_clk_div0 =0x14131440; the      +     //4 Setting up the PLL -     //FOUT = mdiv*fin/(pdiv*2^ (SDIV-1)) =0x7d*24/(0x3*2^ (1-1)) =1000 MHz theRreg_apll_con0 =Apll_val;Bayi     //FOUT = mdiv*fin/(pdiv*2^sdiv) =0x29b*24/(0xc*2^1) = 667 MHz theRreg_mpll_con =Mpll_val; the      -     //5 setting various clock switches, using the PLL -RREG_CLK_SRC0 =0x10001111; the}

Reference Source: Master Zhu's IoT tutorial

Part III: s5pv210_ Clock part _1