Perfect Ethernet switch networking with FPGA

Ethernet switches are still quite common. So I studied how to use FPGA to achieve Ethernet switch networking perfectly. Here I will share it with you, hoping it will be useful to you. Ethernet networking is one of the fastest growing technologies in the industrial market. Most industrial Ethernet standards use the IEEE 802.3 standard Ethernet protocol.

Therefore, these networks can transmit standard network services and real-time data. However, each standard uses different technologies to provide real-time performance. Some use customized hardware, some use customized software, and others use fully standard Ethernet/TCP/IP. As a result, there are many incompatible standards with different levels of performance and costs.

An increasingly popular strategy for non-deterministic Ethernet communication time is to implement a local clock in each device. Because most devices have microprocessor and (relatively) High Speed clock, this method is easier to implement. If accurate clock synchronization can be realized and maintained throughout the network, and the precise operation time series of the entire system can be controlled at the same time, the only limit of this method is the communication latency and the clock synchronization precision within the system range.

This system control method is not suitable for applications such as precise motion control (for example, precise control of motor speed with constantly changing loads), because they require short communication latency between the Controller and the device, however, it is useful for precise control of the entire system that requires highly synchronous system-level control (such as speed changes) (such as a large printing plant or a long automated production line. If you have enough time to send an instruction to each device, the only restriction on the clock-based control accuracy is the clock synchronization accuracy within the system. Several industrial network standards (not just Internet-based standards) are adopting the IEEE1588 standard to provide such control capabilities. IEEE1588 provides a highly accurate master clock and verified clock synchronization mechanism, which can be used to generate all local clocks and maintain very accurate system-level synchronization with the master clock.

Ethernet-based networks are favored for their low cost and easy implementation of Ethernet. Ethernet switches are a key component that helps to take advantage of these benefits, and enterprise systems rely heavily on them for high-performance and easy-to-maintain infrastructure. The large market of Ethernet switches means they are easy to implement and cost-effective. However, most Ethernet switches on the market are not designed for low-latency performance or deterministic routing time, therefore, it is difficult to use it in industrial environments.

The IEEE1588 system detects the communication delay between the host and the slave to synchronize the clock of the host and slave. Placing a switch between the host and the slave clock introduces extra latency because the Ethernet switch must analyze the data packets and then route them. The added latency is not a good thing, but it can be corrected by latency, so it is not the main problem. The biggest problem is that when traffic increases, the time required to route data packets will increase dramatically.

This is due to the time required to cache, analyze, and route data packets to many destinations. This change greatly reduces the accuracy of Clock Synchronization by 1588, thus significantly degrading the real-time control performance of the entire system. The measurement of the latency between the 1588 master and slave clock also relies on the symmetry of the communication time in two directions, because the measurement method is used to calculate a time mark information from the clock to the main clock and then from the main clock to return from the clock time divided by 2. In most Ethernet switches and Ethernet network implementations, this symmetry is unlikely, further reducing the accuracy of clock synchronization.

However, the IEEE1588 standard provides a solution to this problem: If the Ethernet switch itself also has a clock, it can measure the time required for data packet routing and integrate it into synchronous computing. Because the system does not need such a function, it is hard to see Ethernet switches that contain such 'boundary clock. Even if they are, they are generally very expensive and generally customized for a specific network. With the rapid popularization of IEEE1588-based networks, manufacturers are facing huge challenges in how to efficiently and cost-effectively implement the IEEE1588 function in product and network infrastructure.

Developing custom ASIC solutions is possible. However, as the development cost of ASIC increases and the Industrial Ethernet standard changes rapidly, developing such solutions is slow, risky, and cost-effective. You can also use a microprocessor and a third-party ASIC or ASSP for a specific network protocol to develop a solution for each protocol, but this means implementing a separate solution for each network standard, this is also expensive and inefficient. These solutions may also face problems such as lack of flexibility and the rapid expiration of devices. Currently, designers can only avoid the above restrictions by carefully implementing the network, minimizing the use of Ethernet switches, or minimizing the network traffic with strong real-time performance. Such network isolation measures can reach the acceptable performance level for some applications, but they are difficult to implement or maintain.

Save development time

Implementing an Ethernet switch supporting IEEE1588 using FPGA is an ideal solution to this problem. Altera, National Semiconductor, and MorethanIP, directors of each exhibition, the three companies jointly provide an optimized eight-port switch design for Industrial Ethernet designers, this design can shorten the project development time by six to nine months. The cost of development time will lead device manufacturers to take the lead in product time-to-market.

The Ethernet MAC kernel with 1588 scheduled control and programmable uplink functions and the IP address of the switching matrix kernel are developed by MorethanIPGmbH. The MorethanIP enterprise system also provides UDP and 1588 software protocol stacks that can run on a 32-bit AlteraNiosIIRISC processor soft core. To provide the best physical interface, the eight-port ethernet switch is designed with four dual-port PHY transceiver for the National Semiconductor enterprise system.

The reference design has the clock synchronization capability of less than NS and can be used in various applications. The precision of this level is critical to meeting the demanding communication latency and Quality of Service (QoS) requirements required by industrial connections. The target applications include Ethernet switches using Ethernet/IP, ProfiNet, EthernetPowerlink, and other Ethernet protocols.

Product Lifecycle Extension

FPGA's programmable capability is the key to the above design advantages. Starting from a single hardware platform, designers can easily implement Ethernet switches that support different industrial Ethernet protocols (such as EtherCAT and ProfiNet. This development board supports different industrial Ethernet protocols in the same system or from the same Ethernet port.

This is achieved by implementing different media access controller (MAC) hardware modules and embedded processor software to support different Ethernet standards and IEEE1588 functions. The ability to easily reuse previously designed capabilities and availability of ready-to-use IP addresses means that compared with the design using ASIC or ASSP devices, FPGA-based design can generate a configuration that supports new features in a short time. FPGA loads hardware configurations and embedded processor software from a serial flash memory. In the production process, even after the device is delivered to the site, you can easily modify the hardware and software functions of FPGA by rewriting the Flash content.

The programmable hardware and software processing capabilities in FPGA mean that designers can integrate the required additional functionality by using applications as hardware or software. By simply programming FPGA, the ability to implement new functions is a guarantee for the future of the product (for example, supporting IEEE1588v2.0), and new features can be presented to customers very quickly.

Because FPGA has a long life cycle, device manufacturers do not have to worry about potential device end-Information risks. Because the design is IP-based, it is also convenient to transplant the design to the next-generation FPGA, so that designers may benefit from the lower cost or higher performance of the next-generation FPGA product. In addition, the ability to easily perform on-site upgrades makes FPGA Implementation the best way to easily obtain support for product development throughout the product cycle. This reference design uses Altera's StratixIIFPGA, allowing all nioⅱ processor code to be stored in On-chip memory. However, systems with lower costs can be implemented using the CycloneIII FPGA Devices of The Altera enterprise system.