PHY Chip AR8033 Learning Notes

"Introduction to the Chip"

AR8033 is the 4th generation 10/100/1000mbps Rate Ethernet PHY chip of Atheros company, which can be used for home gateway, Enterprise switch, mobile base station, optical module and other equipments. The chip uses the RGMII protocol or the SGMII protocol to communicate with the MAC chip, only need a single 3.3V power supply, can transform the circuit of the chip to other power supply. AR8033 also has a serdes interface with a working frequency of 1.25GHz, which can be connected directly with the optical fiber transceiver module to convert the optical signal into an electrical signal suitable for 1000base-x/100 BASE-FX transmission mode or a SGMII protocol signal for communication with the MAC chip.

The PHY chip belongs to the lowest physical layer in the OSI protocol stack, and the diagram of the other layers is as follows:

Fig. 1 The working position of PHY chip is at the OSI bottom

From the hardware, the general PHY chip is a modular hybrid circuit, responsible for receiving electrical and optical analog signals, after demodulation and A/D conversion through the Mii interface to the signal to the MAC chip for processing. The general Mac Chip is a pure digital circuit.

"SerDes Interface"

SerDes is the abbreviation of the Serializer (serial)/deserializer (the string-picker). It is a mainstream division multiplexing (TDM), Point-to-Point (Peer-to-peer) serial communication technology, that is, at the transmitter end of the multi-channel Low-speed parallel signal is converted into high-speed serial signal, through the transmission medium (optical cable or copper wire), and finally at the receiving end of the high-speed serial signal converted to low-speed parallel signal.

"Rgmii Interface"

Rgmii, reduced GMII, is a simplified version of GMII. Its interface signal line number is 14 (COL/CRS port status indicator signal, which is not drawn here), the clock frequency for the 125MHZ,TX/RX data width of 4 bits, in order to keep the transmission rate of the 1000Mbps unchanged, the Rgmii interface in the rise of the clock along and descent along both sampling data. The reference clock rises along the sending Gmii interface in the txd[3:0]/rxd[3:0], where the reference clock drops along the txd[7:4]/rxd[7:4 of the sending Gmii interface. The RGMII is compatible with the 100Mbps and 10Mbps two rates, at which point the reference clock rate is 25MHz and 2.5MHz, respectively.

Figure 2 Rgmii interface

The tx_en signal line transmits tx_en and tx_er two kinds of information, in the tx_clk of the ascent along the sending Tx_en, the descent along the sending tx_er; Similarly, RX_DV signal lines also transmit RX_DV and rx_er two kinds of information, which are sent rx_clk along the RX_DV's ascent, Descent along the sending Rx_er.

"Sgmii Interface"

Sgmii is serial GMII, is the interface between PHY and Mac, clock frequency 625MHz, send and receive each pair of differential signal line, so the total data rate of 1.25Gbps = 625mbps* 2. Gmii and Rgmii are parallel, and need to follow the road clock, PCB wiring is relatively troublesome, not suitable for backplane applications, and Sgmii is serial, do not need to provide another clock, Mac and PHY use CDR to restore the clock. Reference clock RX_CLK provided by the PHY, is optional, in the clock signal rising along and down along both sampling, mainly for Mac side no clock situation, under normal circumstances, RX_CLK not used, send and receive from the data can be recovered from the clock.

Figure 3 Sgmii interface diagram

In the serial data sent by TXD, each 8bits data is inserted into Tx_en/tx_er 2bits control information, and in RXD receive data, each 8bits data is inserted into the Rx_dv/rx_er 2bits control information, called the 8B/10B code.

"Mdc/mdio Interface"

The interface has MDC and Mdio two lines. MDC is the reference clock signal provided by the Mac, Mdio is a two-way transmission of the configuration data line, with the MDC clock for asynchronous transmission. The AR8033 Mdio interface is a leaky output, so the external pull 1.5k resistor is required for use. The Mdio data frames are composed as follows:

Figure 4 Mdio Data frame structure

The meanings of each field are as follows:

The PRE's response to the MDC clock signal is used to correct the asynchronous transmission clock, which is 32 digits 1.

ST data frame start identification.

OP opcode, 10 for read data, 01 for write data.

Phyad PHY chip Physical address, a total of 5 bits, of which 3 bits can be configured within AR8033.

The Regad register address, a total of 5 bits, is used to select one of the 32 registers in the PHY chip.

TA is used to prevent the creation of a new connection during data transfer, totalling 2 bits. During the reading operation, the 1th position is high resistance, the 2nd digit is 0, the 1th digit of the write operation is 1, and the 2nd bit is 0.

Data represents a total of 16 bits that are read from a register or written to a register. The transmission starts at a high level.

IDLE the idle signal between frames, which shows a high impedance state. There should be at least 1 clock idle signals between adjacent two frames.

"Working mode Configuration"

AR8033 can work in 3 types of modes: Electric port mode, optical port mode, photoelectric Converter mode. Depending on the 4-mode selection of the pin level, the AR8033 can be configured to different operating modes. The official documentation describes the following:

Figure 5 Mode Selection Pins

Fig. 6 Pin level of the light port mode

As you can see from the documentation, when we want AR8033 to work in the 1000Mbps light port mode, we should put the RX_DV, RXD2, RX_CLK, RXD3 these 4 pins of the level down and pull up to 0010. Similarly, to work in the 100Mbps light port mode, you can set the level to 0110 or 1110.

"Application Example"

We can use AR8033 to manage the optical orifice. According to the official data manual, the following structure can be used:

Fig. 7 AR8033 Fiber module system block diagram

It can be seen from the block diagram that when the AR8033 chip is used in the fiber module management, it needs to be configured into 100BASE-FX mode or 1000base-x mode, and the data transmission between the switch chips is rgmii protocol. In practical application, the working mode of AR8033 is configured directly by the main control chip via Mdc/mdio bus, and the data transmission path is AR8033 passed to the switching chip, and then transmitted to the main control chip by the exchange chip. The schematic diagram is as follows:

Fig. 8 AR8033 application diagram

In the schematic, we can see that the data transmission between the optical module chip AR8033 and the switching chip uses the RGMII protocol, the Exchange chip and the main control chip data transmission use SGMII protocol.

"Code Analysis"

About the AR8033 device and driver registration process and code is written here, but the feeling content and the title is relatively independent, so separate out for an article "PHY Chip AR8033 driver code analysis."