Physical Layer Design for FPGA Implementation of SATA host protocol

Next, I will explain the implementation of the SATA host protocol's physical layer.

Is the physical layer structure given in the standard SATA protocol document. It contains the control module, clock data extraction unit, synchronous character source and synchronous character detection module, and analog front-end. The control module coordinates and controls the Logic Functions of the entire physical layer, and provides control signals and status information interfaces to the upstream protocols. The clock data extraction module extracts clock data information from the serial data stream. The synchronous character source and synchronous character detection modules are responsible for byte alignment during the parallel/parallel string conversion process. The analog front end includes a high-speed differential data transmission receiver and OOB Signal Detection and generation circuit.

The figure above looks complicated, but if you have a good understanding of the physical layer protocol and have some knowledge of the altgx transceiver mentioned in the previous blog, we will find that this transceiver has helped us implement clock data extraction units, synchronous character source and synchronous character detection modules, and analog front-end modules. What we need to do is how to configure this transceiver. In addition, an important task of the physical layer is to use the OOB (out of band) signal to identify the device and initialize the device upon power-on. Therefore, the physical layer module is further divided here to obtain the following physical layer diagram. The entire physical layer is divided into four modules, OOB generation and detection, altgx transceiver and physical layer state machine.

First, let's talk about the altgx transceiver. The specific structure of this transceiver is not described in detail here. For details, refer to the statixiv device manual. Here, I just want to explain why I used it. We know that the most common FPGA processing speed is only a few hundred megabytes, but the transmission speed of sata1.0 serial data streams has reached 1.5 Gbps, this speed cannot be directly implemented in FPGA, and SATA finally transmits a differential signal over the transmission line. Here there is a process of numerical simulation, this is not what FPGA can do. The above two problems are not only encountered when implementing the SATA protocol, but also many high-speed serial transmission protocols, such as PCIe, used for FPGA implementation. FPGA vendors generally integrate dedicated hardware into FPGA chips to support this high-speed serial transmission protocol, this kind of dedicated hardware is usually a set of serializer/parsers (serDes) that meet high-speed data transmission rate requirements and a simulated front-end. These integrated dedicated hardware can be configured flexibly to support different communication protocols. The altgx transceiver of Altera belongs to this type, and rocketio Mgt of Xilinx also belongs to this type. The altgx Transceiver can be generated through the IP Configuration Wizard in the quartuⅱ software. For the configuration process, see the article "Implementing SATA and SAS protocols in the Altera device. The configuration is described in detail in this document.

Next, let's talk about the OOB signal. The out-of-band signal, that is, the OOB signal is a set of signals unique to the physical layer. It is implemented by transmitting a set of signals in a specific format on the data line. There are three OOB signals: comreset, cominit, and comwake. The comreset and cominit signals form the same, but the conreset is sent by the host, and the cominit is sent by the device, they are used to identify SATA devices on the host before a normal communication link is established. For the composition of these three signals, refer to the SATA Protocol documentation. Here we will mainly talk about how to implement these signals. We should note two special signal ports during the altgx configuration process. One is rx_signaldetect and the other is tx_forceelecidle. We mainly generate and read OOB signals by controlling these two ports. After reading the SATA documentation, we know that the OOB signal is actually composed of the burst signal and the idle cycle on the data line. The burst signal cycle is better understood, and specific primitives (alignp) are transmitted on the differential data line) what does the idle period mean? A simple understanding is that data is not sent. How does it mean that data is not sent? The analysis of the port tx_forceelecidle has some inspiration. This port is used to forcibly set the sender in altgx to a high impedance. The original "high impedance" means no data transmission. Do not assume that the sender sends "0" as a idle period, "0" also represents a data! On the contrary, it is easy to understand at the receiver end. For differential signals, setting a threshold level detection circuit at the receiver end can distinguish between "with or without" signals on the differential data line, that is to say, the signal that reflects the threshold detection result is rx_signaldetect. In this way, we can understand the specific implementation of the OOB signal. When sending the OOB signal, we can set or reset the tx_forceelecidle port to send the idle and burst signal periods to receive the OOB signal from the device, check the signal level of the rx_signaldetect port to determine whether the current device sends an idle cycle or a burst signal cycle. When the port is set to a bit, it indicates that the device receives an emergency signal cycle. Otherwise, the device is idle. Note that the signals on these two ports are valid at a high level, which means that tx_forceelecidle is idle for high power, while rx_signaldetect is idle for low power. This 1.1 must be noted that this definition is not the same as the signal level definition in Xilinx FPGA. I suffered a loss here. The next step is to implement OOB generation and detection modules. What we need to do is to generate and detect a set of high-level circuits that comply with OOB signal specifications.

Finally, let's talk about this physical layer state machine. The physical layer state machine is the brain of the entire physical layer circuit. It is mainly responsible for controlling the three modules mentioned above, and completes the host's identification of SATA devices and the establishment of communication links during power-on. The following sequence diagram shows the host initialization process during power-on. First, the host sends a comreset signal. After the device receives the message, it responds to cominit. After receiving the message, the host sends a comwake message and then responds to the message. After four OOB signals are interacted, the host completes the identification of the SATA device. Then, the host and the device use the alignp primitive to perform speed negotiation and establish the communication link. After the communication link is established, it is maintained with syncp. For detailed descriptions, refer to the descriptions in this section.

　　

Based on the sequence diagram above, I have designed the following state machine. Its state transition diagram is shown for your reference.

　　

The physical layer has 12 statuses, as shown in the status transition diagram. After the host is powered on, you must first reset the altgx transceiver so that the CDR can be successfully locked to the received data. After the reset is complete, the state machine can receive the power_rst_done signal, and the state machine enters the comreset State to enable the OOB signal generation module to send the comreset signal. If the device receives the comreset signal, the device sends the cominit signal to the host. After the host receives the cominit signal, the state machine sends the comwake signal to enable the sending module to send the comwake signal, then the host waits for the device to respond to the comwake signal. After receiving the comwake signal, the host sends d10.2 data for a period of time to the device until the alignp primitive sent by the device is detected. In this case, the host stores the alignp primitive and returns it to the device at the same rate to complete the speed negotiation. The device sends the syncp primitive to the host. After receiving the primitive, the host enters the link_ready status, indicating that the communication link has been established.

Shows the implementation of the entire physical layer. This is the signal waveform captured by signaltapii. The first is OOB signal transmission, that is, tx_forceelecidle port control signal, the second is OOB signal reception, that is, rx_signaldetect port signal, and the third is altgx receiving 16-bit parallel data after conversion, the fourth is the 16-bit parallel data sent by altgx.

Now, the basic logic of the physical layer is designed. The next article will explain the link layer design.