PMU performance analysis Series 1-related concepts

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1. What is PMU?

Performance Monitor Unit: a performance monitoring unit. In fact, a unit provided by the CPU belongs to the category of hardware. Some performance data of the CPU can be read through access-related registers. Currently, most CPUs provide corresponding PMUs. The following describes the PMUs of Intel series CPUs.

2. Main references:

To learn about PMU, for system programmers, refer to the introduction in Intel 64 and IA-32 ubuntures software developer manuals (volumn3, chapter18 & chapter19 ).

For performance tools such as vtune, you only need to understand the relevant PMU events and refer to the tool documentation.

3. PMU event Classification

Architectural performance events: Compatible among processor families, which is compatible with different processors.
Non-Alibaba tural performance events:Model-specific, That is, model-related, different types of processors have different events.

Some of the very old processors do not have the volume tural event.

Of course, events of the architectural category provide the concept of a version. Different Processors may support different versions, so it doesn't mean that all processors that support the specified tural event support the same number of repeated tural events.

Note: The architectural event was introduced in Intel Core solo and Intel Core Duo processors.

4. Obtain PMU event count

System programmers may need to obtain the PMU event count of the CPU, which can be read using registers such as cpuid, Cr (control register), and MSR (model specific registers. Generally, performance analysis tools provide performance data by analyzing CPU events.

5. About fix counter and programmable counter

Fixed counters and programmable counters. These two words are often seen in relevant documents. Some events are obtained through fixed counters, and some (mostly) are obtained through programmable counters. Refer to 18.4.1 fixed-function performance counters to learn about fixed-function counters. The differences in hardware are not clear, and no documentation is found .) Generally speaking:

As mentioned above, events are classified into invalid tural events and non-trusted tural events. The number of events supported by each processor is relatively small, architectural events can be collected through general-purpose performance counters (common function performance counters) or fixed-function performance counters (fixed function performance counters). The number of non-Architectural events is relatively large, unlike different processors, non-container tural events are generally collected through common performance counters. Visible, fixed
The overall proportion of counter quantity is less.

PS: Fixed counter corresponds to three events: unhalted core cycles, unhalted core reference cycles, and instructions retired. The number of real-time weekly periods, the number of reference clock periods, and the number of valid commands.

6. Impact of hyper-threading on performance event count

In performance counting, it is recommended that you do not enable HT because some events are kernel-based and some events are thread-based. Enabling HT will make the technical results more complex. This is why some processors have cpu_clk_unhalted.core events, while some are cpu_clk_unhalted.thread.