PowerPC ppc460-s MMU (six Shadow TLB)

• • Overview
  • Utlb
  • Shadow TLB
  • DTLB and Itlb
  • Updation

Overview

The definition, properties, and differences between Utlb and Shadow TLB are also briefly described in article I.
This article describes the characteristics of the shadow TLB separately.

Utlb

The so-called utlb here refers to the set of Basic 64 page table entry for the MMU.

Shadow TLB

As is known by the article One, shadowtlb is just to improve the hit efficiency of the page table, one on the hardware resource level
The common TLB cache, similar to cache, is the shadow TLB because the values of these cached tlb are actually derived from
To Utlb (that is, the value of the Shadow TLB is a subset of utlb)

DTLB and Itlb

Since ppc460s in order to avoid the confusion of reference and value, there are also two groups of Shadow TLB;
A set of dtlb (data Shadow tlb) that can cache 8 data TLB Entry;
A group of itlb (instruction Shadow tlb), can cache 4 command TLB Entry;

As long as the entry of the reference or value can be hit in the shadow tlb, the instruction execution process does not exist
If the requested address is not found in the shadow TLB, the Utlb lookup is valid and
The pre-instruction or data access is automatically stopped, and the value is re-taken after it is found in utlb (of course, this
Will waste 3 instruction cycles than the direct lookup utlb); If not found in utlb, the kernel will receive a
To a missing pages exception.

Updation

Seeing such a good design, the problem is coming, how are these shadow tlb groups updated?
In fact, as mentioned before, Shadow TLB is a hardware kernel resource, which means that its replacement or update
is actually done by hardware (based on a round-robin mechanism).
When the shadow TLB has a page fault and is hit in utlb, the hardware automatically replaces the oldest cache with the current
A TLB entry to cache;

In addition, when a system context synchronization occurs, the hardware automatically expires all shadow TLB entry caches;
The common context synchronization directives are as follows:

• Interrupt
• isync directive
• RFI (Exit external interrupt) or RFCI(Exit critical interrupt)
• SC System invoke command

Attention:
Some operations may not cause the hardware to automatically perform contextual synchronization. For example, when we pass the tlbwe directive
When updating the Utlb page table, the hardware does not automatically perform contextual synchronization, that is, the shadow register is not automatically invalidated
Cache (if there is a page table in the shadow cache that has already been invalidated, if there is a new
May cause an unknown problem); If you want to make the update of the utlb or the related PID update can be
In the shadow TLB (guaranteed not to cache stale page tables), it requires the software to proactively
Performs a context synchronization operation (invoking the associated instruction), and it is also necessary to ensure that the instruction does not exist until the command is called
Utlb any access operation (that is, the synchronization instruction must be executed immediately after the update).

Copyright NOTICE: This article for Bo Master original article, without Bo Master permission not reproduced.

PowerPC ppc460-s MMU (six Shadow TLB)