Principle and Application of fractional division and fast lock chip ADF4193

Principle and Application of fractional division and fast lock chip adf4193

[Date: 2008-12-5]

Source: Electronic Components application Author: Wang Fang, read yonghong

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0 Introduction

In the design process of digital mobile communication systems, frequency hopping is often used to improve the communication system's anti-interference and multi-path fading ability. However, this requires that the ultra-fast frequency hopping PLL in the fast frequency hopping system be able to stabilize to the required phase and frequency within dozens of microseconds (μs. To meet this requirement, the "ping-pong" architecture can be adopted. However, this structure requires two frequency synthesizer. When one frequency synthesizer works as lo, the other frequency synthesizer is used to lock the frequency required by the next step. And now. You can also use a quick lock chip. The adf4193 fast-switching frequency synthesizer produced by the American ADI company uses a PLL fast lock chip. It can meet the switching index of the "ping-pong" structure, so it can be used in the lo circuit of the radio transmitter and receiver's upper-frequency conversion and lower-frequency conversion circuit.

1 adf4193 features and working principle of PLL

Adf4193 is a fast lock chip based on Fractional division. The main features of this chip are as follows:

◇ It has a rapidly adjusted Decimal-N phase-locked loop structure;
◇ Single-Chip PLL can be used to replace switch synthesizer;
◇ 5 μs frequency hopping can be achieved in the GSM band, and the phase can be stabilized within 20 μs;
◇ 2 GHz output with 0.5 phase error;
◇ Programmable output phase;
◇ The RF input range is up to 3.5 GHz;
◇ With 3-line serial interface;
◇ The chip has a built-in low-noise differential amplifier;
◇ The phase noise sensitivity can reach-216Hz/Hz.

ADF4193 is mainly based on the frequency hopping principle of the "ping-pong" architecture. As shown in principle 1 of ADF4193, in the figure, VCO is used to provide a reference frequency fx. fx gets the reference frequency of the phase detector input end through pre-Division R, the function of the loop filter in Figure 1 is to filter out the high-frequency components and noise of the output signal of the phase detector, and convert the output current of the phase generator to the voltage to the input end of the VCO. To control the output frequency of VCO. At the same time, the VCO output frequency is fed back to the phase detector after N-division. The phase detector is used to compare the feedback frequency and reference phase frequency. When the two input signals of the phase detector are synchronized (and fvco/N = fr, the output frequency of VCO is the frequency to be locked.

In the formula, the frequency N is an integer or decimal number.

2. Influence of divider on PLL indicators

2.1 Phase Noise

In general, the frequency divider has a greater impact on the relevant metrics of the PLL than N. This section describes the effect of Phase Noise and lock time. Factors that affect phase noise include division ratio, Phase Identification frequency, inherent background noise of PLL, and closed-loop transfer function. The neighborhood of the neighborhood can be expressed as follows:

In formula, PN/Hz indicates the inherent background noise of the PLL. N indicates the division ratio, and fcomp indicates the Comparison Frequency;

From the formula (2), we can see that in the channel, phase noise is mainly determined by the phase detector. When the phase frequency fcomp doubles, the corresponding value is halved, and the output frequency remains unchanged, the phase noise can improve by 3 dB. Therefore, in order to reduce the phase noise in the pass band, we should try to use the PLL with a lower division ratio during design.

2.2 lock time

The lock time is closely related to the closed-loop bandwidth. The larger the loop bandwidth, the shorter the lock time, the smaller the loop bandwidth, and the longer the lock time. For the second-order ring, the lock time T ∝ 1/ω ε (where ω is the loop bandwidth and ε is the damping factor ). Therefore, you can change the lock time by changing the loop bandwidth value.

For integer division, the loop bandwidth can be up to 1/10 of the reference frequency fr. Therefore, the method of changing the lock time by loop bandwidth alone has great limitations.

For fractional division, the selection of loop bandwidth is basically less relevant to the reference frequency FR, and the reference frequency of fractional division can be very large. For example, the FR of adf4193 can be set to 13 MHz. If the bandwidth is calculated by 1/10, the loop bandwidth can be as wide as 1.3 MHz, so the selection of the fractional-division loop bandwidth is almost not considered Fr.

Although the wider the loop bandwidth, the shorter the lock time, the larger the loop bandwidth, the worse the filtering effect, the lower noise of the PLL output frequency is higher.

When the loop is locked, there is usually a fixed phase difference between the reference clock and the regeneration clock. If the difference is assumed to be △t, the formula for calculating the phase error is as follows:

Vtune is the tuning end voltage of VCO or vcxo, in V; ipump_out is the output phase current of the phase detector, in Ma; fcomp indicates the phase frequency, in kHz; zvco is the input impedance of VCO or vcxo, in ohm.

From formula (3), we can see that the phase difference between the reference clock and the regeneration clock should be as small as possible, the main factor is that the phase identification frequency of the system and the input impedance of the oscillator are large enough. The scope of △t is closely related to locking. Most PLL chips require that the absolute Phase Error of three or five phases in a row be less than 15 NS at the lock time. Otherwise, the lock is deemed as a loss. Select three or five phases. You can set them through the corresponding registers. During the lock period, the phase error of any period is greater than 25 NS, that is, the lock is lost.

In general, loop bandwidth, lock time, and phase noise affect and constrain each other. To obtain a short lock time, a large loop bandwidth is required, but more noise is introduced, which may lead to deterioration of the phase noise. Similarly, if a good phase noise is required, the loop bandwidth will be reduced and the lock time will increase. If you want to improve the phase noise without changing the loop bandwidth, follow the formula (2) to make some improvements in the divider IV and Phase Identification frequency fcomp.

3 FPGA configuration process for adf4193

You can use FPGA to configure adf4193. Adf4193 has eight registers. By configuring these eight registers, adf4193 can be enabled to work normally. Adf4193 has a three-line serial interface, which is Le, CLK, and data. Data can be input from the 3-line serial interface of adf4193 to the 24-bit input shift register, with the high byte in front of the clock increase. When the enable signal Le is extended, the data in the shift register will be locked into eight registers R0 ~ One of R7. The specific register can be determined by the three control bits C3, C2, and C1 of the 24-bit percentile of the shift register.

The Initialization Configuration data can be sent to the Register corresponding to adf4193 in a certain way to implement initialization of adf4193. Figure 2 shows the configuration map captured by the logical analyzer.

Figure 2 shows the 17-step configuration process of adf4193. The values of registers R0 and R2 determine the output frequency of the Phase-Locked Loop. In Figure 2, After configuring the first two registers, it takes 10 ms to discharge the capacitance of the loop filter. With this configuration, you can configure adf4193 on any desired frequency. Note that the frequency hopping operation can be performed only when the initialization process is stable. Otherwise, adf4193 will not be able to perform the normal frequency hopping function.

Figure 2 shows the configuration sequence of the first configured register, as shown in figure 3.

As shown in figure 3, configuring data for a register can be controlled through the Le signal. When le is low. Exactly 24 clock cycles are stuck in the first drop delay of Le and within the next increase delay. From the last three digits of the data, we can see that the register for this configuration is R5. The configuration process for other registers is the same.

4. PLL metric measurement

4.1 phase noise measurement

The output phase noise of adf4193 can be measured using the phase noise template of the instrument. The Measurement Result 4 is shown.

From figure 4, we can see that freq offset can achieve good performance at: 100Hz, 1 kHz, 10 kHz, 100 kHz, and 1 MHz.

4.2 lock Time Measurement

To save costs, ad8302 provided by ADI can be used and the locking time can be measured with an oscilloscope. The measurement principle structure based on ad8302 is shown in Figure 5.

The actual use proves that the adf4193 lock time can reach the required indicator. In addition, the configuration of adf4193 is relatively simple and easy to implement using FPGA, and the performance can be ensured at the same time.

5 conclusion

According to the configuration sequence of adf4193, adf4193 is a configuration-easy and usable chip that can simplify the design complexity and shorten the project debugging cycle. From the measurement results of Phase Noise and lock time, we can see that adf4193 has good performance indicators and better stability. The main advantage of adf4193 is that it can easily implement frequency hopping. It no longer needs to use the "ping-pong switching" circuit, thus shortening the switching time of the system, to implement frequency switching within the time slot protection period. Facts have proved that adf4193 can simplify the circuit, reduce costs, and save the PCB layout area. It is suitable for communication systems.