Principle and application of microcomputer exercise library and answer

Principle and application of microcomputer exercise library and answer

Exercises and Exercises 1

The 1th Chapter Introduction

1. Computers are divided into those categories. What are the characteristics of each.

A: Traditionally divided into three categories: large mainframe, small machine, microcomputer. Large-scale mainframe is generally high-performance parallel processing system, large storage capacity, the ability to handle things, can provide services for many users. Minicomputer has certain data processing ability, provide a certain user-sized information service, as the Department of Information Service center. Microcomputer generally refers to the desktop or mobile computing system in the office or home, small size, low price, with an industrial standard architecture, good compatibility.

2. Briefly describe the connotation of three terms of microprocessor, microcomputer and micro computer system.

A: Microprocessors are the core hardware components of micro computer systems, which have a decisive impact on the performance of the system. Micro-computer includes microprocessor, memory, I/O interface circuit and system bus. Micro computer system is based on the micro-computers with the corresponding external equipment and a variety of software, to form a complete, independent information processing system.

3. The 80x86 microprocessor has several generations. What the names of the generations are.

A: From the architecture can be divided into 3 generations: ¬8080/8085:8-bit machine. 8086/8088/80286:16-bit machine.

®80386/80486:32-bit machine.

2nd chapter microprocessor structure and micro-computer composition

1. 8086 is how many bits of microprocessor. Why.

A: 8086 is a 16-bit microprocessor, its internal data path is 16 bits, the external data bus is also 16 bits.

2. What are the respective functions of the EU and Biu? How to work together.

A: EU is the execution part, the main function is to execute the instruction. The Biu is a bus interface component that transmits data to the off-chip memory and I/O interface circuitry. The EU provides access to the Biu for off-chip operations and BIU the EU with instructions to be executed. The EU and Biu can work independently, and Biu can populate the command queue when the EU does not need BIU to provide services.

3. 8086/8088 What is the improvement in internal operations compared to the previous generation of microprocessor 8085.

A: 8085 is a 8-bit machine, during the execution of the instruction, the command and execution of the order are serial. 8086/8088 due to the internal EU and biu two functional components, can overlap operation, improve the performance of the processor.

4. 8086/8088 the internal microprocessor has those registers, what their main role is.

A: The execution part has 8 16-bit registers, AX, BX, CX, DX, SP, BP, DI, SI. AX, BX, CX, DX are generally used as general data registers. The SP is a stack pointer, and BP, DI, and Si are used as address registers or as variable addresses when indirectly addressing. The bus interface parts are provided with segment registers CS, DS, SS, es, and instruction pointer register IPs. The segment register holds the address of the segment, together with the offset address to form the physical address of the memory. The content of the IP is the offset address of the next instruction to be executed, together with CS to form the physical address of the next instruction.

5. 8086 why a segmented approach is used to manage memory.

A: 8086 is a 16-bit structure, using a segmented management approach to form a memory physical address of more than 16 bits, extending the addressable range (1mb,20 bit address) of the memory. Without the segmented method, the 16-bit address can only be addressed in 64KB space.

6. In 8086, the logical address, the offset address, and the physical address respectively refer to what. Specific instructions.

A: The logical address is a representation of the memory address in the program, consisting of the segment address and the offset address in the segment, such as 1234h:0088h. An offset address is a 16-bit binary code that refers to the difference between a storage unit in a segment relative to the first address of that segment. The physical address is the 20-bit address code sent out by the 8086 chip leader to indicate a specific storage unit.

7. Given a memory unit that holds data, the offset address is 20c0h, (DS) =0c00eh, and the physical address of the memory unit is calculated.

Answer: Physical Address: 320f8h.

8. 8086/8088 why address/Data leader Multiplexing technology is used.

A: Considering the cost of the chip, 8086/8088 adopts 40-lead package structure. 40 leads lead out 8086/8088 of all signals is not enough, the use of address/data line multiplexing Lead method can solve this contradiction, from a logical point of view, the address and data signal will not appear simultaneously, the two can be used to reuse the same group of leaders.

9. The main difference between 8086 and 8088 is what.

A: 8086 has 16 data signal leads, 8,088 only 8, 8086 in-chip instruction prefetch buffer depth is 6 bytes, 8,088 only 4 bytes.

10. How to determine the maximum or minimum operating mode of 8086. How do the maximum and minimum modes produce control signals differently

A: The logic state of the lead mn/mx# determines the operating mode of 8086, the mn/mx# leads are high, the 8086 is set to the minimum mode, the mn/mx# leads are low, and 8086 is set to maximum mode.

The control signal in the minimum mode is provided directly by the relevant lead, and the control signal in the maximum mode is provided by the 8288 special chip, 8288 of the input is 8086 s2#~s0# three status signal lead.

11. After 8086 is reset, the status of the register is what. Where the microprocessor starts executing the program.

A: The flag register, IP, DS, SS, es, and command queue 0,cs all 1. The processor takes instructions from the FFFFOH storage unit and begins execution.

12. 8086 how the basic bus cycle is composed. What basic operations are done in each state.

A: The basic bus cycle consists of 4 clock (CLK) cycles, defined in chronological order as T1, T2, T3, T4. During T1 8086 sends the address signal of the access destination and the address latch-up radio number ALE;T2 during the reading and writing command signal rd#, wr# and other related signals; data access is completed during T3; T4 ends the bus cycle.

13. The function of ale, m/io#, dt/r#, rd#, Ready signal is illustrated by the bus operation sequence diagram in 8086 min mode.

A: Ale is the strobe pulse of the external address latch, output during T1, m/io# determines whether the bus operation object is a memory or I/O interface circuit, the T1 output, dt/r# for the direction of the data bus buffer control signal, in T1 output; rd# for read command signal; in T2 output The ready signal "prepares" the signal for the memory or I/O interface, given during T3, or 8086 to insert the TW wait state between T3 and T4.

14. 8086 interrupts are divided into which two classes. 8086 the number of interrupts that can be handled.

A: 8086 interrupts can be divided into two categories, hardware interrupt and software interrupt. 8086 can handle 256 types of interrupts.

15. 8086 What is a masked interrupt request input line. What is the meaning of "masking"?

A: The masked interrupt request input line is intr; "masking" means that the interrupt request can be disabled by the software to clear the IF bit in the flag register.

16. How the 8086 interrupt vector table is composed. What the role is.

A: The 0~3FFH area in memory 0 is used as the dedicated storage area of the interrupt vector table. This area holds the entry address of 256 types of interrupt handlers, each with 4 storage units, each with a segment address and an offset address for the entry.

17. 8086 how to respond to a masked interrupt request. Briefly describe the response process.

A: When 8086 receives INTR high level signal, under the current instruction execution and if=1 condition, 8086 in two bus cycles respectively emits the inta# valid signal; During the second inta#, 8086 receives a byte interrupt type code from the interrupt source ; 8086 complete the operation of the protection site, CS, IP content into the stack, except if, tf;8086 the type code by 4 to get the entry address of the interrupt vector table, starting from the address to read 4 bytes of the interrupt handler entry address, 8086 from this address to start the execution of the program, The response process for the INTR interrupt request has been completed.

18. What is a bus request. 8086 in the minimum operating mode, what is the signal pin for the bus request.

A: If there are more than one main module in the system to control the bus, one of them to use the bus for data transmission, the system needs to request the bus control, which is a bus request process. 8086 the signal pin for the bus request in the minimum operating mode is hold and Hlda.

19. A brief description of how 8086 responds to a bus request in the minimum operating mode.

A: The external bus master module sends a bus request signal to 8086 through the hold lead, 8086 samples the hold leader on the rising edge of each clock cycle, and if hold=1 is found to emit a response signal from the bus request at the end of the current bus cycle (T4 end) hlda;8086 the address, Data and control bus enter a high-impedance state, give up the bus control, complete the response process.

20. In a 8086-based micro computer system, how the memory is organized. is how to connect to the processor bus.

What is the function of the bhe# signal.

A: 8086 is a 16-bit processor, access to 1M bytes of memory space, 1M bytes of memory is divided into two 512K bytes of storage, named even-byte body and odd-byte body, even the data line connection d7~d0, "body select" Signal Address line A0; The data line connection of the odd body D15~d8, "body selection" The signal is connected to the bhe# signal, and the bhe# signal is valid to allow access to high-byte storage units in the singularity, enabling 8086 of low-byte access, high-byte access, and word access.

21. "80386 is a 32-bit microprocessor", the meaning of this sentence refers mainly to what.

A: The 80386 data bus is 32 bits, the on-chip register and the main function parts are 32 bits, the on-chip data path is 32 bits.

22. What are the benefits of 80x86 series microprocessors that take technical routes that are compatible with previous microprocessors. There is no shortage.

A: The advantage is that previously developed software can be run in a system consisting of a new processor, protecting the software investment. The disadvantage is that the structure of the processor is constrained by compatibility, which increases the cost of silicon resources and increases the complexity of the structure in order to maintain compatibility.

23. 80386 The internal structure consists of which parts. Describe the role of each part.

A: 80386 the internal structure consists of the actuator (EU), the Memory Management Unit (MMU) and the Bus interface components (BIU) three parts. The EU includes instruction prefetching components, instruction decoding components, control components, operational components, and protection inspection components, the main function of which is to execute instructions. The memory management part includes the segmented part, the paging part, realizes the management of the segmented paging of the memory, and translates the logical address into the physical address. The bus interface component acts as an off-chip access: Access to memory and I/O interfaces, prefetch instructions, and control of bus and interrupt requests.

24. 80386 There are several memory management modes. What it is.

A: 80386 has three kinds of memory management mode, namely real address mode, protection mode and virtual 8086 mode

25. What is the role of 80386 segment registers in different memory management modes?

A: In the field site mode, the segment register is the same as 8086, storing the subgrade address. In the protection mode, each segment register also has a corresponding 64-bit segment descriptor register, and the segment register holds the selector as a selector. In virtual 8086 mode, the segment register functions the same as 8086.

26. Try to explain the meaning of virtual memory, which is different from physical memory. 80386 How large the virtual address space is.

A: Virtual memory is a huge, addressable storage space that the programmer faces, which is formed by the combination of memory and external memory, and under the management of the operating system, the program can access the external memory as much as it accesses the memory to obtain the required data. Physical memory refers to the internal memory that the machine actually owns, not including the external memory. The 80386 virtual address space is 64TB large.

27. The classification of descriptors and the function of each descriptor are described.

A: Descriptors are divided into three categories: Memory segment descriptor, System segment descriptor, door descriptor. The memory segment descriptor consists of 8 bytes, which is used to describe the situation in which information is saved in a segment. The 32-bit segment base address and the 20-bit segment boundary value position the segment in the storage space, and other relevant bits determine the access rights and the length units of the segment. The system segment descriptor is the same as most byte segments of the memory segment descriptor, with some differences in access rights and attribute byte segments. The gate descriptor is used to change the program's privilege level, the execution of the switch task, and the entry that indicates the interrupt service program.

28. What is the role of the descriptor descriptor. There are several types of descriptor tables.

A: The descriptor list holds a series of descriptors that define all the memory segments that are used in the 80386 system. There are 3 types of descriptor tables, the Global Descriptor table, the local descriptor list, and the interrupt descriptor.

29. How the segmented part of 80386 changes the logical address to a linear address.

A: The segment part extracts the corresponding segment descriptor from the Global descriptor table or the local Descriptor table based on the segment selector. The linear address is formed by adding the segment descriptor 32-bit segment base address to the 32-bit offset in the logical address.

30. How to turn a linear address into a physical address in 80386.

A: The 32-bit linear address formed by the segmented part has a high of 10 bits as the offset of the Addressing page catalog table, and a 32-bit address is formed in the page directory table of the control register CR3 to a page item in the page table, which is a page descriptor. The height of the page item is 20 bits as the page base address, the low 12 bits of the linear address is the offset, and the addition forms a 32-bit physical address that points to a storage unit. When paging is disabled, the linear address is the physical address.

31. 80386 how interrupts are categorized.

A: 80386 interrupts are divided into two categories: external interrupt and internal interrupt, external interrupt input request signal via NMI and intr lead. Internal interrupts are also called internal abnormal interrupts, which can be divided into trap interrupts, abnormal internal faults, and abnormal termination interrupts.

32. 80386 The Interrupt Descriptor table is different from the 8086 interrupt vector tables in the protection mode.

A: 8086 work in the field site mode, the vector table is in the memory of 0 segments in the lowest 1024 bytes of memory. 80386 in the protection mode to access the interrupt vector of the virtual space by the descriptor in the Interrupt Descriptor table, the location of the interrupt descriptor tables is not fixed, and the IDTR register is implemented in the virtual space.

33. This paper briefly describes the process of interrupt processing in 80386 under protection mode.

A: 80386 after the response is interrupted, receive the type code provided by the interrupt source and multiply it by 8, and add to the base address in the IDTR register, indicate the position of the interrupt descriptor, read out the interrupt descriptor, depending on the segment selector and conditions determine from two descriptor list LDT or a GDT to get the segment descriptor, The linear address of the memory unit where the Interrupt Service program entry is formed.

Exercises and Exercises 2

3rd 8086 instruction System and addressing method

1. Write an assembly language program according to the following requirements:

(1) The segment name of the code snippet is Cod_sg

(2) The segment of the data segment is named Dat_sg

(3) The segment name of the stack segment is STK_SG

(4) The variable High_dat contains 95 of the data

(5) Load variable high_dat into register AH,BH and DL

(6) The entry address of the program operation is start

Answer:

Dat_sg segemnt

High_dat DB 95

Dat_sg ENDS

;

Stk_sg SEGMENT

DW "DUP" (?)

Stk_sg ENDS

;

Cod_sg SEGMENT

MAIN PROC Far

Assume Cs:cod_sg, Ds:dat_sg, Ss:stk_sg

Start:mov AX, DAT-SG

MOV DS, AX

MOV AH, High_dat

MOV BH, AH

MOV DL, AH

MOV AH, 4CH

INT 21H

MAIN ENDP

Cod_sg ENDS

END START

2. Indicate the error in the following procedure:

STAKSG SEGMENT

DB DUP (?)

Sta_sg ENDS

Dtseg SEGMENT

DATA1 DB?

Dtseg END

Cdseg SEGMENT

MAIN PROC Far

Start:mov ds,datseg

MOV al,34h

ADD AL,4FH

MOV Data,al

START ENDP

Cdseg ENDS

END

Answer:

After correction:

STAKSG SEGMENT

DB DUP (?)

STAKSG ENDS

Dtseg SEGMENT

DATA1 DB?

Dtseg ENDS

Cdseg SEGMENT

MAIN PROC Far

Assume Cs:cdseg, ds:dtseg, SS:STAKSG

Start:mov Ax, dtseg MOV DS, Ax

MOV AL, 34H

ADD AL, 4FH

MOV DATA1, AL

MOV AH, 4CH INT 21H

MAIN ENDP

Cdseg ENDS

END S

3. Fill in the following file types into spaces:

(1). obj (2). EXE (3). CRF (4). ASM (5). LST (6). Map

The editing program output file has ______________________________________;

The assembler output file has ______________________________________;

The file that the connector outputs is ______________________________________.

Answer:

Edit Program Output file: (4)

Assembler Output file: (1), (3), (5)

Connector output file: (2), (6)

4. What is the following label illegal?

(1) GET. DATA (2) 1_num (3) Test-data (4) RET (5) NEW ITEM

Answer:

Illegal marking: (1) because '. ' Allow only the first character of a label