Principle and Application of Si4133 integrated with Phase-Locked Loop Chip

Principle and Application of Si4133 integrated with Phase-Locked Loop Chip

[Date: 2008-9-3]

Source: China Power Grid Author: Liu huaping, Guo Wei

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Introduction

Frequency synthesis technology is the main signal source of modern RF microwave systems. Currently, digital frequency synthesizer is widely used, which is generally composed of crystal oscillator, divider, phase detector, filter and VCO (voltage controlled oscillator, the standard frequency signal is obtained by dividing the frequency signal output by the crystal oscillator, and then compared with the frequency signal output by VCO in the phase detector to generate loop lock control voltage, the voltage is added to the VCO through a filter to control and correct the VCO output signal until the loop is locked.

1. Phase-Locked Loop Frequency Synthesis chip and working principle

Figure 1 shows the basic module of the Digital Phase-locking frequency synthesizer chip. It contains three-way PLL ). Each PLL consists of PD (phase detector), LF (loop filter), VCO, and programmable divider.

Taking 1-way PLL as an example, the operating principle of the chip is briefly introduced. Refer to the frequency fin to input people from the XIN foot and get the frequency fin/R through the amplifier and R divider. At the same time, after the output frequency fout of this VCO passes through an N divider, the frequency fout/N is obtained. Two frequencies are transmitted to PD for phase comparison to generate an error control voltage. The Error Voltage passes through the DC component of an error signal within LF and serves as the input of VCO, it is used to adjust the output signal frequency of VCO, so that the signal frequency fout/N to fin/R after VCO division is near equal until the last two frequencies are equal, and phase synchronization achieves locking. When loop locks are performed, the input frequency difference of PD is 0, that is, fin/R = fout/N, fout = Nfin/R, you can change the frequency of the output signal by changing the Division coefficient N of the output signal and the Division coefficient R of the reference signal.

The center frequency of the three-way pll vco is determined by the external inductance. The PLL can adjust the output frequency within the range of VCO center frequency ± 5%.

There are two channels in the three-way PLL for RF output. These two RF plls are time-division multiplexing, that is, only one PLL works within a given period of time. During each rf pll operation, the RF output frequency can be adjusted within the center frequency of VCO. Therefore, the RF output can be controlled by simply programming the corresponding N divider, and then work in two independent frequencies. The two rf vco center frequencies are optimized between 947 MHz and 1.72 GHz, and between 789 MHz and 1.429 GHz.

The third PLL is used for intermediate frequency synthesis. the center frequency of the VCO of the circuit can be adjusted by the external inductor connected to the IFLA and IFLB pins. The intermediate frequency output of the PLL can be adjusted within ± 5% of the VCO center frequency. The Inductance Value is inaccurate and can be compensated by the automatic adjustment algorithm of Si4133. The central frequency of the intermediate frequency VCO can be adjusted between 526 MHz and 952 MHz. IF necessary, you can reduce the IF output frequency by dividing the frequency.

In addition, the chip uses serial programming control, and the peripheral circuit is very simple and easy to use.

2. Frequency Source Design and Application Example

2.1 Frequency Source Circuit Design

As shown in Principle 2 of the frequency source circuit with Si4133 as the core, this circuit can generate 900 MHz RF (RF) signal and 550 MHz IF (IF) signal.

The 12 MHz high-stability active crystal oscillator is used as the reference frequency source. RF output signals must be coupled to the load through capacitor AC. The intermediate frequency output pin must also be coupled to its load through a capacitor AC. The external inductor range of RF 1 channel is 0 ~ 4.6nH; the external inductance range of RF 2 channel is 0.3 nH ~ 6.2 nH; the external inductance range of the intermediate frequency is 2.2 nH ~ 12.0 nH. When selecting an inductor, consider calculating the internal inductor according to the resonance frequency f =.

2.2 VCO center frequency setting

The center frequency is determined by the external inductor value connected to the respective VCO. Considering that the external Inductance Value has a deviation of ± 10%, the Si4133 algorithm can be used to compensate the inductance error. Because the Inductance Value is nH order of magnitude, encapsulation must be considered when determining the Inductance Value. The total inductance Ltot of each VCO is the sum of the external inductance Lext and the encapsulation inductance Lpkg. The total inductance is connected to a nominal capacitor, as shown in 3.

The formula for calculating the center frequency is:

2.3 Software Control for serial interfaces

Si4133 has 16 22-bit data registers, ranging from 0 ~ Registers 8 are programmable. They are: main configuration register, phase detector gain register, Power Loss Register, RF 1 and RF 2 N divider register, if N divider register, RF 1 and RF 2 R divider register, if R the divider register. Register 9 ~ Register 15 is reserved and not written. Each register has 22-bit serial characters including 18-Bit Data codes and 4-bit address codes. By writing registers through serial communication, you can set the RF, IF frequency, and frequency division coefficient of the reference frequency, obtain the RF and IF frequencies required at the end, and control the gain (also known as Phase sensitivity) of PD ). By setting the PWDN pin level and internal registers, you can set low-power working modes of RF and IF respectively, and select the circuit to work. The AUXOUT pin can output frequency out-of-lock signals. VCO gain and LF gain are not programmable.

3 Test Results

In the finished circuit test, set the phase frequency of the reference frequency source to 200 kHz. The test shows that there is a stray frequency at 200 kHz from the center. The performance indicators of the frequency source are as follows: the output power is 0.18 dBm at MHz, the phase noise at 10 kHz, 50 kHz, and 100 kHz offset is-69 dBc/Hz,-85 dBc/Hz, and-105 dBc/Hz, respectively, the output power is 200 dBm when the offset between 400 kHz and 1.4 kHz is-72 dBc and-79 dBc: 0.22 cHz, respectively, the offset of Phase Noise at 10 kHz, 50 kHz, and 100 kHz is-67 dBc/Hz,-84 dBc/Hz, and-103 dBc/Hz, respectively, the offset of stray suppression at 200 kHz and 400 kHz is-70 dBc and-74 dBc respectively. Likewise, it has good performance when the intermediate frequency is 550 MHz. The phase noise of the Frequency Source is low, the stray signal is well restrained, and the output frequency bandwidth is large.

In the design of the PLL frequency synthesizer, the phase noise should be considered to reach the circuit indicator to eliminate the effect of the phase noise. Generally, the in-band phase noise of the loop is determined by the noise of the phase detector, divider, and crystal oscillator, while the out-of-band phase noise is mainly determined by VCO. For phase noise of the crystal oscillator reference source, M divider, phase detector, and N divider, the transfer function is low-pass. For VCO, the transfer function of phase noise is high-pass. Therefore, the total output phase noise is the superposition of the noise source phase noise and their respective transfer function products. In addition, the loop bandwidth has a great impact on the intra-loop noise, if the loop bandwidth is too narrow, the in-band noise of VCO cannot be ignored. However, if you select an excessively wide value, the out-of-band noise will deteriorate.

4 Conclusion

The design of the frequency source with the Si4133 frequency synthesizer chip as the core is simple, and the output frequency value can be controlled by the software, which is very convenient and has low phase noise and low stray noise. Various indicators can meet the design objectives.