Principle and example of S3C2410 DMA

1. DMA meaning: Direct Memory acess, which can exchange data between high-speed and I/O devices and memory without the control of the CPU.
 
2. S3C2410A supports 4-channel DMA and can be run in the following four cases
 
① Both the source device and target are on the system bus AHB.

② Both the source device and target are on the peripheral bus APB.

③ The source device is on the system bus, and the target device is on the peripheral bus.

④ The source device is on the peripheral bus, and the target device is on the system bus.
 
3. Transmission Protocol
 
① Single-step mode: One DMA transmission has two DMA response cycles (two response signals nxdack are generated) to indicate the DMA Read and Write cycles. It is mainly used in the test and debugging modes. Before the Read and Write cycles, bus control can be granted to other bus Controllers

② Continuous mode: a DMA request will generate continuous DMA transmission until the specified DMA transmission data is completed, and the nxdack will remain valid during the DMA transmission period. The DMA request signal is released. After each data unit is transmitted, the control of the bus is released to allow other bus controllers to occupy the bus.

4. DMA Operation
 
DMA uses a three-state FSM (Finite State Machine) for operations. The following three steps are described:

State-1: initial state. The DMA waits for the DMA request. If the request arrives, it enters state 2. In this phase, the dma ac and INT req are 0

State-2: The DMA Ack is changed to 1, and the value of the counter curr_tc is loaded from dcon. DMA ack remains 1 until it is cleared.

State-3: Initialize the sub-FSM (sub-state machine) that performs atomic operations on DMA. Sub-FSM reads data from the source address and writes the data to the target address. For this operation method, the data size and transmission size should be considered. In the overall service mode (whole service mode), this operation is repeated until the counter curr_tc is changed to 0, but only once in a single mode. When the sub-FSM completes each atomic operation, the master FSM is counted as curr_tc. In addition, when curr_tc is 0 and dcon [29] is set to 1, the primary FSM sends an int req (interrupt request signal) and clears the DMA ack if any of the following conditions occur

① In the overall service mode (whole service mode), curr_tc is changed to 0.

② Complete the single service mode atomic operation

In single mode, the three statuses of the primary FSM are stopped and wait for another DMA req. If the DMA req arrives, three States are repeated. Therefore, each atomic operation is performed after the DMA Ack is declared.

On the contrary, in the overall service mode (whole service mode), the primary FSM waits 3 until the curr_tc changes to 0. Therefore, DMA ack performs atomic operations when the TC reaches 0 after it is declared in the transmission interval.

Some of my friends may have questions about "Atomic operations". I have not found a standard definition. In my understanding, operations are uninterrupted. You must complete this operation before performing other operations. On the contrary, in the overall service mode (whole service mode), the primary FSM waits 3 until the curr_tc changes to 0. Therefore, DMA ack performs atomic operations when the TC reaches 0 after it is declared in the transmission interval.
Some of my friends may have questions about "Atomic operations". I have not found a standard definition. In my understanding, operations are uninterrupted. You must complete this operation before performing other operations.

5. There are three types of external DMA request/response protocols

① Single Service Demand ② single service handshake ③ whole service handshake

The differences between the demand and handshake modes are mainly the xnxdreq and xnxdack time series. datasheet has specific instances.

 

6. Operation settings

① DMA channel initialization: rdisrc, rdisrcc, rdcon0, rdidst, rdidstc, rdmasktrig0

② DMA interrupt Initialization

③ Set the DMA request source. For example, set UART to the DMA format rucon0 = rucon0 & 0xff3 | 0x8;

④ Set the DMA interrupt service program

Instance:

// ------------ System initialization ---------------------------------------------------------------

 

1 // set the system frequency
2 changeclockdivider (); //
3 // changempllvalue (0x5c, 0x200, 0x00); // fclk = MHz
4 changempllvalue (0x7d, 0x266x1); // fclk = MHz mpllcon
5 void appdmainit (void)
6 {
7 // rintmod | = (1 <17); // [17] int_dma0: 0 = IRQ, 1 = FIQ
8 // pisr_dma0 = (INT) dma0done; // interrupt the service program of dma0
9 pisr_dma1 = (INT) dma1done; // interrupt the service program of dma1
10 // rdisrc0 = tsrc_addr;
11 rdisrc0 = (0 <1) | (0 <0); // Inc, AHB source from AHB
12 // rdidst0 = 0x31100000;
13 rdidst1 = 0x10000000;
14 rdidstc1 = (0 <1) | (0 <0); // Inc, AHB for AHB
15 rdcon1 = (0 <31) | (1 <30) | (1 <29) | (1 <28) | (1 <27) | (1 <23) | (0 <22) | (1 <21) | (0 <20 );
16 // | (rdcon0 & fff00000) | 0x80); // demand mode, whole service mode, burst mode
17 // 31 bit 1: handshake Mode 0: demand mode is selected.
18 // 30-Bit 0: synchronization between dreq and Dack and APB clock 1ahb
19 // 29-bit 1: 0-curr_tc interrupt is disabled
20 // 28-bit transfer size of an atomic transfer 0: a unit transfer 1: A burst transfer of length four is saved med.
21 // 27-bit 1: the entire service mode is 0.
22 // 23 bits 0: S/W request mode selected, DMA plus 3 bits by setting the sw_trig bit of the dmasktrig register
23 // 1: select the DMA source through [26:24] triggers the DMA Operation
24 // 22-bit 1: when the current value is 0, the DMA channel (MDA req) is turned off when the transfer count. 0: automatically reload
25 // bits 00 = byte 01 = half word 10 = word 11 = Reserved
26 // [19:0] initial transfer count (or transfer beat ).
27 rdcon1 = (rdcon1 & 0xf8f00000) | 0x20; // 1word * 4 (burst) * 32 = 128 word
28 // rdcon1 & = 0xf8ffffff; // [26:24] = 000 dcon1: 000: nxdreq1 dcon0: 000: nxdreq0
29 rgpedat = (rgpedat & 0xfff5) | 0x5;
30 rgpecon = (rgpecon & 0xffffff00) | 0x00000055;
31 // assign the first address
32 src = (byte *) graph_start_adrr;
33
34}
35
36 interrupt Initialization
37
38 static void _ IRQ dma1done (void) // dma1 interrupt (dmadone)
39 {
40 // unsigned char I = 100;
41 clearpending (bit_dma1 );
42 src = SRC + 512;
43 rdisrc1 = (INT) SRC;
44 // dma1done = 0;
45 // uart_printf ("DMA is % x! \ N ", rdisrc1 );
46
47}
48

DMA waveform sampling with FPGA: