Principle and Implementation of simple frequency division-counters

In a digital system, clock pulses of multiple frequencies are often used as the driving source. In this way, the FPGA system clock frequency (high frequency) needs to be divided.

For example, you cannot directly use the system clock (too fast to be identified by the naked eye) when designing a flow lamp or digital tube dynamic scan, or when you need to communicate with each other,

Because the communication speed cannot be too high (limited by different standards), it is necessary to divide the system clock to get a lower frequency clock.

The divider is mainly divided into even-number, odd-number, half-integer, and Fractional-number. If parameterized design is adopted during the design process, you can change the parameters at any time to obtain different frequency division requirements.

In FPGA systems that do not have very strict clock requirements, the frequency division is usually achieved through the cyclic counter count.

Even Division (2n)

Even Frequency Division is the most simple, it is easy to use the module for n counter to achieve 50% duty cycle of the clock signal, that is, each count of N (counted to the N-1) when the output clock signal flip.

Odd Division (2n + 1)

Using a counter with a modulo of 2n + 1, let the output clock flip each time in the X-1 (x between 0 and 2n-1) and 2n, an odd number of divider can be obtained, however, the duty cycle is not 50% (x/(2n + 1 )).

The basic idea of getting an odd-number divider with a duty cycle of 50% is:Rising edge triggerThe counter's odd-number crossover output signal clk1, and the obtainedDescent edge triggerThe same count (Same clock flip Value) Clk2,

Finally, clk1 and clk2Phase orAfter the output, an odd number of divider with a duty cycle of 50% is obtained. The schematic diagram is as follows:

The output signal outclk of the 9-division clock with a duty cycle of 50% obtained using Quartus II is as follows:

Half integer division (N-0.5)

The basic design idea is: first count the modulo n, count to the N-1, the output clock flip; and when the count returns to 0, the output clock flip again.

So, as long as the Count value N-1 to maintain half a clock cycle, you can achieve N-0.5 frequency clock. How can we maintain a half-cycle clock?

Because the counter is the rising edge trigger count, if the counter trigger clock is flipped when the Count value is = N-1, the falling edge of the clock becomes the rising edge. That is, when the Count value = N-1, the clock immediately flipped,

After the Count value is kept for half a clock cycle, the Count value is set to 0 due to a rising edge. then the counter Continues counting with the flipped clock, and the clock is flipped again after the N-0.5 has been generated.

2.5Frequency DivisionThe time sequence is as follows:

How can I make the trigger clock of the counter flip at the N-1? The schematic diagram of the half integer divider shows that the output clock is in the same phase as the input clockExclusive orTrigger the clock flip.

Schematic diagram of a half-integer DividerAs follows:

The 2.5 division Time Sequence Chart implemented by Quartus II is as follows:

The diagram consists of a universal divider circuit. It can be seen that a half-integer divider is composed of an integer divider plus a two-way division and an exclusive OR gate.

Then, if you use the component instantiation idea, you can get a general frequency division (you can select the integer and semi-integer Frequency Division ).

If you want to obtain any frequency division, refer to crazybingo'sUsing DDS principlesTo teach you what is the true random division.