Principle of measuring FPGA and other precision Frequencies

As mentioned earlier, the measurement frequency at the week of measurement has an error of + 1, because the counting does not necessarily start in the starting time of the gate. For example, when the frequency is measured, the relative error is large at low frequencies. Although there is a saying that the frequency measurement is low frequency, it is difficult to determine a limit. Therefore, we need to find a frequency algorithm once and for all.

The same precision frequency measurement can meet the needs. Its biggest characteristic is that the gate time is always an integer multiple of the tested signal period. That is to say, when the gate enables, the actual gate does not start, but the two counters start counting at the same time when the rising edge of the tested signal arrives. When the gate is closed, it is not until the rising edge of the signal arrives. The following sequence diagram (from Baidu Library) demonstrates this.

Here, "counting when the rising edge starts" is easy to implement, that is

Always @ (posedge dataIn)BeginIf (ENA = 1) ...... end

Always @ (posedge clkref)BeginIf (ENA = 1) ...... end

This counting can eliminate the + 1 error. The so-called equi-precision means that the relative error has nothing to do with the frequency itself, and there is no need for high and low frequency concerns. The error depends on the standard signal and can be generated using a phase-locked loop. To further reduce the error, increase the standard signal frequency and increase the Count value.

Final formula: FO/NO = F1/N1.

Principle of measuring FPGA and other precision Frequencies