Principles and Applications of NAND flash in Embedded Systems

Currently, storage modules are indispensable in the development and design of various embedded systems. Nor and NAND are two major non-loss flash technologies on the market.

Nor-flash memory has a small capacity and a low write speed. However, due to its fast random reading speed, it is often used in the storage of program code in embedded systems. The internal structure of nor-flash memory determines that it is not suitable for large-capacity development. The structure of NAND-flash memory can provide an extremely high unit density and achieve a large storage capacity, in addition, the write and erase operations are fast.

Nand flash memory is a type of flash memory. It adopts a non-linear macro unit mode internally, providing a cheap and effective solution for the implementation of Solid State large-capacity memory. Nand flash memory has a large capacity and a fast rewrite speed, and is suitable for storing a large amount of data. Therefore, it has been widely used in the industry, for example, embedded products include digital cameras, MP3 flash memory cards, and Compact USB flash drives. This article takes Samsung's k9f1208uob chip as an example to introduce the read/write process and timing of the nand flash memory chip.

 1 operating principle of nand flash memory

1.1 Structure and Instruction Set of nand flash memory

The capacity of k9f1208uob is 64 mb. The storage space consists of 528 K pages (rows) and bytes (columns) on each page. The remaining 16 columns are located in 512-527 of the column address. K9f1208uob also divides the storage space into blocks, each of which consists of 32 pages. Therefore, k9f1208uob contains 4096 blocks. This "block-page" structure can meet the structure requirements of the file system for clustering and sector partitioning. The internal structure 1 of k9f1208uob is shown in.

Figure 1 internal structure of k9f1208uob

The read and write operations of k9f1208uob are in the unit of page, and the erased operation is performed in the unit of block.

The k9f1208uob address is transmitted through an 8-bit port, which effectively reduces the number of pins and ensures the consistency of the pins of devices of different density, the system can be upgraded to a high-capacity memory without changing the circuit.

K9f1208uob multiplexing of commands and addresses on the I/O port through the CLE and ale signal lines. Commands, addresses, and data are written to the device by lowering the we and Ce ports. Some commands only need to be completed in one bus cycle, such as reset commands, read commands, and status read commands. Other commands, such as page writing and block erasure, require two cycles, one cycle is used for start, and the other is used for execution.

1.2 NAND Flash operations 1.2.1 page read Operations

During initial power-on, the device enters the default "Read mode 1 ". In this mode, the page read operation is started by writing the H command into the instruction register and then writing three addresses (one column address and two row addresses. Once the page READ command is locked by the device, the following page read operation does not need to write the command again.

After writing commands and addresses, the processor can analyze the signal line R/B to determine whether the operation is complete. If the signal is low, the device is "busy". If the signal is high, the internal operation of the device is completed and the data to be read is sent to the data register. The external controller can read data from the I/O Ports sequentially under the control of a continuous re pulse signal with a period of 50 ns. In the continuous page read operation, the output data starts from the specified column address until the data of the last column address on the page.

1.2.2 page write operations

The write operation of k9f1208uob is also in the unit of page. The write operation must be erased. Otherwise, the write operation will fail.

The page write cycle consists of three steps: writing the serial data input command (80 h), writing the Three-byte address information, and writing the data in sequence. A maximum of 528 bytes of data can be written in serial mode. The data is first written to the page register in the device, and then the device enters an internal write process to write data from the page register to the storage macro unit.

After writing the serial data, you need to write the "page write confirmation" command 10 h, which will initialize the internal write operation of the device. If 10 h is written separately without the previous steps, 10 h does not work. After 10 h of writing, the internal write controller of k9f1208uob will automatically execute the necessary algorithms and time series for internal writing and verification. Then the system controller can do other things.

After the internal write operation starts, the device automatically enters the read Status Register mode. In this mode, when Re and CE are low, the system can read status registers. You can check the output of R/B or the status bit of the read Status Register (I/O 6) to determine whether the internal write is complete. When the device writes data internally, only the read Status Register instruction and reset instruction are returned. When the page write operation is complete, the write status bit (I/O 0) level should be checked.

The internal write check only checks if no write is successful. The instruction register always maintains the read Status Register mode until other valid instructions are written into the instruction register.

1.2.3 block Erasure

The erasure operation is performed in blocks. The erased start command is 60 h, and the block address input is completed through two clock cycles. In this case, only the address bits A14 to A24 are valid, and A9 to A13 are ignored. After the block address is loaded, run the erasure confirmation command d0h, which is used to initialize the internal erasure operation. The erasure validation command is also used to prevent external interference from accidental erasure operations. After the device detects the input of the erase validation command, the internal write controller is started on the rising edge of we to perform the erasure and erasure verification. After the internal erasure operation is complete, check the write status bit (I/O 0) to check whether there is an error in the erasure operation.

1.2.4 read Status Register

K9f1208uob contains a status register that reflects whether the write or erase operation is complete, or whether the write and erase operations are correct. Write 70 h commands to start the read Status Register cycle. Status Register content will be sent to the I/O port at the CE or Re descent edge.

Once the device receives the read Status Register command, it will keep the Status Register in read status until there are other command input. Therefore, if the status register operation is used in any read operation, the H or 50 H command must be re-issued during the continuous page read process.

1.2.5 read device ID

The k9f1208uob device has a product identification code (ID) that the system controller can read to identify the device. The read ID step is to write the 90 H command and then write the address 00 H. In two read cycles, the vendor code and device code are continuously output to the I/O port.

Similarly, once you enter this command mode, the device will remain in this command State until other commands are received.

1.2.6 Reset

The device provides a reset command to write FFH to the instruction register to reset the device. When the device is busy in any read, write, or erase mode, sending a reset command can stop the device from performing the current operation. The content of the memory macro unit being modified is no longer valid, the instruction register is cleared and waits for the next instruction to arrive. When WP is high, the Status Register is cleared as c0h.

2 system hardware connection and Software Design

2.1 The interface circuit 2 of the hardware connection k9f1208uob and s3c2440a is shown.

Figure 2 k9f1208uob and s3c2440a hardware circuits

2.2 Software Design

Step 1: NAND Flash Initialization

The nandflash_test.mcp project file is created using tools such as ads1.2. The test_k9s1208 sub-function in the NAND. c file implements the main test function. Gpacon = rgpacon; rgpacon = (rgpacon &~ (0x3f <17) | (0x3f <17); first back up the content of rgpacon, and then set the way the GPA17-22 works. Then call the NAND Flash initialization function. Nf8_init0; // source code of the initialization function: rnfconf = (tacls <12) | (twrph0 <8) I (twrph1 <4) | (0 <0): rnfcont = (0 <13) | (0 <12) | (0 <10) | (0 <9) | (0 <8) | (1 <6) | (1 <5) | (1 <4) | (1 <1) | (1 <0 ):

Step 2: Read the device ID

Because s3c2440a does not provide direct and nand flash memory interfaces as it supports SDRAM, the read/write process depends on software programming. After the NAND-flash is initialized, you can perform operations on the NAND-flash. The program calls the nf8_print_id () sub-function to read the device ID code. Id = nf8_checkid (); // continue to call the sub-function device = (u8) ID; maker = (u8) (ID> 8): uart_printf ("maker: % x, device: % x ", maker, device); nf8_print_id () source code: nf_cmd (0x90); // write the 90h command nf_addr (0x0 ); // write address 00 h for (I = 0; I <10; I ++); uart_printf ("nfstat: 0x % x", rnfstat); Id = nf_rddata8 () <8; // maker code 0xec read ID value ID | = nf_rddata8 (); // devide code (k9s1208v: 0x76), (k9k2g16u0m: 0xca)

Step 3: Page read/write Program

This experiment implements the write and read-out verification function for a page. The test_nfs_rw sub-function implements this function.

The program first initializes the data to be written. * dstpt is the data to be read and verified. It must be set to 0 first. * srcpt is the data to be written. It must be filled with a random number.

For (I = 0; I <512; I ++) * dstpt ++ = 0x0; // enter 0 for (I = 0; I <512; I ++) {# If ads10 = true if (offset =-1) * srcpt ++ = rand () % 0xff; // random number filling # else if (offset =-1) srcpt ++ = I % 0xf; # endif else * srcpt ++ = I + offset ;} before writing, perform Erasure: If (nf8_erasebiock (Block) = fail) return; then perform the page write operation: If (nf8_writepage (Block, page, srcpt) = fail) return; write the data pointed to by srcpt filled with random numbers to the specified page. Read verification after writing: If (nf8_readpage (Block, page, dstpt) = fail) return; uart_printf ("checking data. "); For (error = 0, I = 0; I <512; I ++) {If (* srcpt ++! = * Dstpt ++) {// compare uart_printf ("error: % d [W: % x, R: % x]", I, * srcpt, * dstpt ); error ++ ;}} if (error! = 0) {uart_printf ("fail to R/W test (% d ). ", error); Return (2);} else {uart_printf (" r/W test OK. "); Return (1 );}

Nf8_readpage (Block, page, dstpt) puts the read data into the address space pointed to by dstpt. Finally, compare the written data with the read data to print the verification information.

Step 4: compile the project

After all functions are implemented, code them through ads1.2 to generate executable files. In the project folder "andflash_testaandflash_test_datakdebugrel", you can see the nandflash_test.bin executable file.

Step 5: Download the program to run

Connect the serial cable with the serial port of the hardware development system board and the COM1 of the development pc (mainly used for ECHO). Connect the serial cable with the USB port of the development PC (mainly used for data download ), open the dnw software, set the serial port to COM1, the bit rate to 115200, and the USB to 0x30000000.

Use dnw to download the previously generated executable file to the memory for running.

3 conclusion

This article mainly discusses the working principle of the nand flash memory chip and uses Samsung's ARM920T processor core s3c2440a based on ARM as a testing example, this gives readers a comprehensive understanding of the hardware and software design process of the entire storage system, so that they can be used in the design of other embedded systems.

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