Principles of online ICT Testing

Abstract: This article describes the basic knowledge and principles of online testing. 1. Statement 1.1 defines online testing, ICT, in-circuit test, it is a standard test method to check the electrical performance and electrical connection of online components to detect manufacturing defects and component defects. It mainly checks the opening and short circuit of a single online component and each circuit network, and features simple operation, fast and fast, and accurate fault location. Flying needle ICT only performs static tests. The advantage is that no jigs are required and the program development time is short. The needle-bed ICT can be used to test the functions of simulator parts and the logic functions of digital devices. The fault coverage rate is high. However, special needle-bed jigs, jigs, and program development cycles are required for each board. 1.2 The scope and characteristics of ICT inspect the electrical performance of online components and the connection of circuit networks. Ability to quantitatively measure the resistance, capacitance, inductance, crystal oscillator, and other devices, and test the functions of diodes, transistors, optical connectors, transformers, relays, operational amplifiers, and power supply modules, test the functions of Small and Medium-sized integrated circuits, such as all 74 series, memory, common drivers, and switching ICs. It detects Manufacturing Process Defects and component defects by directly testing the electrical properties of online devices. The component class can detect the exceptional, invalid or damaged component values, and program errors of the memory class. For the process type, faults such as Soldering Tin short circuit, component insertion error, plugging back, missing installation, pin climbing, virtual welding, PCB short circuit, and disconnection can be found. The test fault is located directly on specific components, device pins, and network points, and the fault location is accurate. No professional knowledge is required for troubleshooting. Automated Testing with program control is easy to operate and quick to test. The testing time of a single board is generally several to dozens of seconds. 1. 3. Online Testing is usually the first test process in production. It can reflect the manufacturing status in a timely manner, facilitating process improvement and improvement. Fault boards tested by ICT can greatly improve production efficiency and reduce maintenance costs due to accurate fault locating and convenient maintenance. Because of its specific testing project, it is one of the important testing methods to guarantee the quality of modern production. Brief Introduction to ICT testing theory 1 Basic Testing Method 1.1 simulator testing using operational amplifiers for testing. The concept of "A" point "" Virtual Ground "includes: javasix = iref javasrx = VS/V0 * rrefvs and rRef are the excitation signal source and the calculation resistance of the instrument respectively. If the value of v0 is measured, RX can be obtained. If the RX to be tested is a capacitor or inductance, The vs AC signal source, Rx is in the impedance form, and C or l can also be obtained. The above test method of 1.2 isolation (guarding) is for independent devices, and the devices on the actual circuit are connected and mutually affected, so that IX has ref, which must be isolated during the test ). Isolation is a basic technology for online testing. In the above circuit, because of the connection shunt of R1 and R2, the IX branch ref, RX = VS/V0 * rRef equation is invalid. During the test, as long as the G and F points share the same potential, there is no current flow in R2, there is still IX = iref, And the RX equation remains unchanged. Ground the G point. Because the F point has the same potential as the two points, isolation can be achieved. In practice, enable the Equipotential of G and F through an isolated operational amplifier. The ICT tester provides multiple isolation points to eliminate the impact of peripheral circuits on testing. 1.2 IC testing for digital IC, using vector testing. The vector test is similar to the truth table measurement, the excitation input vector, and the measurement output vector. The actual logic function test is used to determine whether the device is good or bad. For example, test the analog IC based on the actual function of the IC to stimulate the voltage, current, Measurement corresponding output, as a functional block test. 2. With the development of modern manufacturing technology and the use of ultra-large-scale integrated circuits, it often takes a lot of time to compile vector testing programs for devices, for example, 80386 of the testing program takes nearly half a year for a skilled programmer. A large number of applications of SMT devices make the failure of open circuits even more prominent. For this reason, the non-vector testing technology of various companies, teradyne launched the multiscan; genrad launched the Xpress non-vector testing technology. 2.1 deltascan analog completion testing technology deltascan uses static electricity discharge protection or parasitic diodes from almost all digital device pins and the vast majority of hybrid signal device pins, perform a simple DC current test on the independent pins of the tested device. When the power supply of a Board is cut off, the equivalent circuit of any two pins on the device is shown in. 1. Add a negative voltage to pin a, and the current IA flows through the forward bias Diode of pin. Measure the current IA flowing through pin. 2. Maintain the voltage of Pin A. Add a high negative voltage to pin B. The current IB flows through the forward bias Diode of Pin B. Because the current in the common substrate resistor from Pin A and B to the ground is shared, the current IA will decrease. 3. measure the current IA flowing through pin a again. If the IA does not change (DELTA) when the voltage is added to pin B, there must be a connection problem. The deltascan software combines many possible pin pairs on the device to obtain accurate fault diagnosis. The signal pin, power supply, ground pin, and substrate are all involved in the deltascan test. This means that in addition to the pin detaching, deltascan can also detect manufacturing faults such as missing devices, plugging backlines, and wire disconnection. Genrad class tests are called junction Xpress. It also utilizes the diode characteristics in the IC, but only tests are achieved by measuring the spectral characteristics (quadratic harmonic) of the diode. Deltascan technology, without the need to attach fixture hardware, becomes the first technology. 2.2 framescan capacitive coupling test framescan disconnects the detecting tube foot by capacitive coupling. Each device is equipped with a Capacitive Probe that inspires a pin and picks up signals from the Capacitive Probe.: 1. On the multi-channel switch board on the fixture, select the Capacitive Probe on a device. 2. The testing board (ATB) in the tester sends an AC signal to each tested pin in turn. 3. capacitive probes collect and buffer the AC signals on the tested tubes. 4 ATB measures the AC signal picked by the Capacitive Probe. If a pin is correctly connected to the circuit board, the signal is measured. If the PIN is detached, no signal is generated. The genrad technology is called Open Xpress. The principle is similar. This technology jigs require sensors and other hardware, and the testing cost is slightly higher. 3 boundary-scan border scan technology ICT tester requires each circuit node to have at least one test point. However, as the integration of devices increases, the functions become stronger and stronger, the packages become smaller and smaller, the SMT components increase, and the density of PCB components increases when multiple layers are used, it is very difficult to place a probe on each node, increasing manufacturing costs to add test points, and increasing development cycles to develop a Test Library for powerful devices. Therefore, the Joint Testing Organization (JTAG) has issued the ieee1149.1 test standard. Ieee1149.1 defines several important features of a scanner. Define four (five) pins that constitute the Test Access Port (TAP): TDI, TDO, tck, TMS, and (trst ). Test Mode Selection (TMS) is used to load control information. Secondly, several different test modes supported by the TAP controller are defined, including extest and intest) runtest. Finally, boundary scan Description Language (Boundary Scan Description Language) is proposed. bsdl describes important information of the scanner. It defines the pins as input, output, and bidirectional types, defines the mode and Instruction Set of the TAP. Each pin of a device with a boundary scan is connected to a serial shift register (SSR) Unit, called a scan unit. The scan unit is connected together to form a shift register chain, used to control and Detect Device pins. Its specific four pins are used to complete the test task. Connect the scanning chains of multiple scanners through their tap to form a continuous boundary register chain, you can add a tap signal to the chain head to control and detect the pins of all connected devices. This virtual contact replaces the physical contact of each pin of the needle bed fixture. virtual access replaces the actual physical access and removes a large amount of testing pad that occupies PCB space, reduces the cost of PCB and fixture manufacturing. As a testing strategy, when conducting testability design for PCB boards, you can use specialized software to analyze circuit outlets and devices with scanning functions to determine how to effectively put a limited number of test points, without reducing the test coverage rate, the most economical reduction of test points and test points. The boundary scan technology solves the difficulty of adding test points. More importantly, it provides a simple and quick way to generate test images, software tools can be used to convert bsdl files into test images, such as teradyne's victors, genrad's basic scan and scan path finder. Solve the difficulty of compiling complex test libraries. Using the tap access port, you can also implement online programming (in-system program or on board program) for CPLD, FPGA, and Flash memroy ). 4 NAND-treenand-tree is a design technology designed for testability by Inter. In our products, only the 82371 chip is found in this design. There is a general *. tr2 file describing its design structure. We can convert this file into a test vector. ICT testing requires accurate fault locating and stable testing, which is closely related to circuit and PCB design. In principle, we require a test point for each circuit network point. In circuit design, the status of each device must be isolated, which does not affect each other. Testability requirements should be installed for the design of the border scan and NAND-tree.