Processing problems of the Tilde inout signal... 1
FPGA Description:... 1
The program I wrote:... 1
Test. v. 1
Simulation waveform... 2
Feelings... 2
FPGA description:
Bidirectional Signal
First of all, I would like to describe a basic knowledge. In FPGA design, bidirectional signals can only be used in input and output, but bidirectional signals cannot be used in internal logic. Do not use this signal. Otherwise, the tool will combine something you don't know.
For a two-way port, You need to convert it into an input signal in, an output signal: Out, and an output enabling signal: output_enable.CodeIt is actually very simple:
Assign birsignal = output_enable? Out: 1 'bz;
Assign in = birsignal,
Here is a small tip: When writing code, you suddenly do not know how to write the syntax, you can right click in Quartus, you can find an insert template... . Try it.
I wrote Program : Test. v
Module test
(
Input CLK, // CLK Input
Output Reg Oe, // output enable
Output Reg [3: 0] CNT, // counter
Inout [1:0] data, // input and output data
Input [1:0] data_in, // data for input
Output [1:0] data_out, // data for output
Output Reg [1:0] dout // output plugin
);
Always @ (posedge CLK) // counter
Begin
CNT <= CNT + 1' B1;
If (CNT = 7)
OE <= ~ OE;
End
Assign DATA = Oe? Data_in: 2 'bzz;
Assign data_out = data;
Reg [1:0] counter;
Always @ (posedge CLK)
Begin
Case (Counter)
0:
Begin
Counter <= 1;
Dout <= 2 'bzz;
End
1:
Begin
Counter <= 2;
Dout <= 2 'bzz;
End
2:
Begin
Counter <= 3;
Dout <= 2' B11;
End
3:
Begin
Counter <= 0;
Dout <= 2' B00;
End
Endcase
End
Endmodule
Simulation waveform
Feelings
Remember, when an inout bidirectional data is encountered, it should be divided into two parts,
Assign DATA = Oe? Data_in: 2 'bzz;
Assign data_out = data;
This simplifies the problem and is not prone to errors.