Procedures of U-boot

The U-boot process can be dividedTwo Stages)

The following is a flowchart of the U-boot startup process. The left and right sections are the two phases of the boot process.

Stage 1 ):

Code that depends on the CPU architecture (such as the device initialization Code) is generally usedAssemblyLanguage. Configure the following items:Set arm to enter SVC Mode,Disable IRQ and FIQ,Disable the dog and shield all interrupts..Set clock(Fclk, hclk, pclk ),Clear I/D cache, clear TLB, disable MMU and Cache,Configure the memory controller, prepare for code migration, and move the uboot image to ram.(Using copy_loop ),Allocate stacks and clear BSS segments(Implemented using clbss_l ).

(1) specific settings and code implementation:

ÜSet arm to enter SVC mode, disable IRQ and FIQ

The bit allocation in the CPSR register (and the spsr register that saves it) is as follows:

  31 30 29 28  ---  7  6  - 4  3  2  1 0 

  N  Z  C  V I F M4  M3 M2 M1  M0 

 00000User26 Mode 

 00001Fiq26 Mode 

 00010Irq26 Mode 

 00011Svc26 Mode 

 10000User Mode 

 10001FIQ Mode 

 10010IRQ Mode 

  1110011SVC Mode 

 10111Abt Mode 

 11011Und Mode 

To set the SVC mode, you need to set the first disconnection to six IRQ (interrupted) and seven (fast interruption) bits.;

Mrs r0, CPSR@ Read the CPSR value to R0 Bic r0, R0, # 0x1f @ Clear M0 ~ M4 ORR r0, R0, #0xd3 @ Disable IRQ and FIQ interruptions and place the processor in the management mode (svc32 Mode) Msr cpsr, R0@ Return the R0 value to CPSR

Disable the dog and shield all interrupts.

# If defined (config_s3c2400) | defined (config_s3c2410) LDRR0, = pwtcon MoVR1, #0x0 StrR1, [R0] MoV R1, #0 xffffffff; All interrupt disabl LDR r0, = intmsk STR R1, [R0] # If defined (config_s3c2410) LDR R1, = 0x3fff; All Sub interrupt disable LDR r0, = intsubmsk STR R1, [R0] # Endif

For the wtcon registers of S3C2440 and S3C2410, the [0] control allows or disables the reset output function of the watchdog timer. It is set to "0" to disable the reset function. By setting intmsk, all interrupt bits of intsubmsk can be blocked.

Set CPU: clear I/D cache, clear TLB, disable MMU and Cache

# Ifndef config_skip_lowlevel_init Cpu_init_crit: @ Initialize caches MoVR0, #0 MCRP15, 0, R0, C7, C7, 0 MCRP15, 0, R0, C8, C7, 0

For more information about arm coprocessor, see ARM920T Technical Reference Manual (Rev 1:

MCR and MRC are commands for operating the ARM processor's coprocessor;

The operation prototype of MCR P15, 0, RD, C7, C7, and 0 is as follows:

Invalidate icache and dcache | sbz | MCR P15, 0, RD, C7, C7, 0

This command invalidates icache and dcache, where icache is the instruction cache and dcache is the data cache. for RD instructions, sbz (shocould be zero ), is to make all the bits in this register are 0, so the first statement is mov r0, #0.

The operation prototype of MCR P15, 0, R0, C8, C7, 0 is as follows:

Invalidate TLB (s) | sbz | MCR P15, 0, RD, C8, C7, 0

This command invalidates TLB. Maybe the reader will ask, what is TLB?
TLB is short for translation lookaside buffers, which is an address decoding action. It can be translated into "address translation traversal cache ". Readers interested in this mechanism can download the instructions of ARM920T Technical Reference Manual (Rev 1) from the official website.
Next, we will disable MMU and caches.

@ Disable MMU and caches MRCP15, 0, R0, C1, C0, 0 BicR0, R0 and #0x00002300@ Clear bits 13, 9: 8 (-- V--- RS) BicR0, R0 and #0x00000087@ Clear bits 7, 2: 0 (B ----cam) OrrR0, R0 and #0x00000002@ Set bit 2 (a) Align OrrR0, R0 and #0x00001000@ Set bit 12 (I) I-Cache MCRP15, 0, R0, C1, C0, 0

In the ARM920T Technical Reference Manual (Rev 1) instructions, you can find the following information:

MRC P15, 0, RD, C1, C0, 0; Read control register MCR P15, 0, RD, C1, C0, 0; Write control register

The first setting command: 0x00002300 = 10001100000000 (B), digits 8, 9, and 13 are cleared, that is, S, R, and V are cleared. According to the ARM920T instructions, the R bit of S is cleared, indicating that any access to MMU will result in domain failure ). The V bit is cleared, indicating the address of base location of exception registers, starting from 0x0.

Second setting command: 0x00000087 = 10000111 (B), digits 0, 1, 2, and 7 are cleared. That is, M, A, C, and B are cleared, indicating MMU disabled, data address alignment Fault Checking, Fault Checking disabled, dcache disabled, and little-Endian operation. When you press the restart key, U-boot checks the storage type of the CPU, whether it is large-end storage or small-end storage. When the 7th-bit value is set to 1, it is big-end storage, when the value of 8th bits is set to 0, it is stored on the small end.
The third setting command:0x00000002 = 10 (B), that is, location 1 of 1st, indicates that the corresponding mode is set to data address alignment Fault Checking and Fault Checking enabled.

Article 4 set the command: 0x00001000 = 1000000000000 (B), that is, 12th position 1, indicates that icache can be enabled, that is, the command cache can be enabled. Then MCR
P15, 0, R0, C1, C0, 0 is to write the corresponding bit operation result to register 1 to make it take effect.

Note: We will not explain the initialization of the first-stage clock here.

Stage 2 is usually implemented in C.

FirstStart_armboot ()The function is the entry point and mainly performs the following operations:

Initialization(CPU, board, interrupt, serial port, console, etc.), openEnable I/D cache. Initialize flash and perform other initialization operations according to the system configuration. Print log, enable interruption, get environment variables, initialize Nic. EnterMain_loop () function. In the main_loop function, the bootdelay and bootcmd environment variables are checked. If bootcmd has been set, the bootcmd will be automatically executed after bootdelay is milliseconds. If the user is interrupted during the waiting process (CTL + C) or bootcmd is not set, the user will wait for the user to enter the command.

At this point, U-boot has been started up normally. If you want to learn more about U-boot, you can analyze the source code. This section will not be more detailed.