Programming method for register configuration __ Programming

struct Register_element codec_init_mic1_loutr_reg[] = {//power down {0x810004,0x00},////assign Syncdomain {0x810 068,0x00},//SDAIF1=SD1, SDAIF2=SD2 {0x810069,0x30},//sdaif3=sd3, sdaif4=sd4 {0x81006a,0x03},//ADC CODEC=3//{0x810 06B,0X33},////{0x81006c,0x33},////{0x81006d,0x33},////{0x81006e,0x33},///{0x81006f,0x33},//#if 0//PLL
	1 setting {0x81003e,0x05},//xti 26MHz {0x81003f,0x00},//pld1 {0x810040,0x06},//pld1 d+1=7 {0x810041,0x00},//PLM1 {0x810042,55-1},//plm1 m+1=39//clock setting//{0x810048,0x21},//MCLK1=PLLCLK1 & Master Mode//{0x810049,0x4f} ,//mbclk1 divider {0x810049,0x4f},//32fs=1536khz//{0x810049,0x27},//bdv1+1=40/cks1/(BDV+1)/64fs=3072kHz//{ 0x81004a,0x1f},//msync1 Divider {0x81004a,0x1f},//fs=48khz//{0x81004a,0x3f},//sdv1+1=64/bclk/(SDV+1)/Fs=48kHZ//A Dded by Huberg {0x81004e, 0x21},//mclk3 = PLL1, master mode {0x81004f, 133-1},//bclk3 = mclk3/(79+1) {0x810050, 0x1F}, WCLK3 = bclk3/(31+1) {0x810064,0x01},//codec Clock source=pllclk1 {0x810065,0x09},//codec mclk divider mdiv2+1=10 {0x810066,0x01},//DSP MCLK=P LLCLK1 {0x810067,0x09},//mclk divd+1=10 bus CLK div/#else//pll1 setting {0x81003e,0x05},//xti 26MHz {0x81003f,0x00 },//pld1 {0x810040,0x07},//pld1 d+1=7 {0x810041,0x00},//plm1 {0x810042,40-1},//plm1 m+1=39,//clock setting//{0 X810048,0X21},//mclk1=pllclk1 & Master Mode//{0X810049,0X4F},//MBCLK1 divider {0x810049,0x4f},//32fs=1536khz//{ 0X810049,0X27},//bdv1+1=40/cks1/(bdv+1)/64fs=3072khz//{0x81004a,0x1f},//msync1 divider {0x81004A,0x1F},//fs= 48kHZ//{0x81004a,0x3f},//sdv1+1=64/bclk/(sdv+1)/fs=48khz//added by Huberg {0x81004e, 0x21},//mclk3 = PLL1, mast Er mode {0x81004f, 80-1},//bclk3 = mclk3/(79+1) {0x810050, 0x1f},//wclk3 = bclk3/(31+1) {0x810064,0x01},//codec Cl Ock SOURCE=PLLCLK1 {0x810065,0x09},//codec mclk divider mdiv2+1=10 {0X810066,0X01},//DSP}, MCLK divd+1=10 bus CLK div/#endIf//added by Huberg {0x810098, 0x00},//dspckadj = 0, dspmclk = dspmclk source* (256-dspckadj)/256//i2s//codec// Changed by Huberg {0x810006,0x0f},//all on//{0x810006,0x03},//pmmp1a pmmp1b=on {0x81001a,0x0a},//fs=48khz, COD  EC Master clock=256fs {0x810020,0x21},//dac1r=rch,dac1l=lch@mixing {0x810021,0x21},//dac2r=rch,dac2l=lch//Added by Huberg//{0x81002e, 0x40},//dac clock//////////////////////////////////////////////////////////////{0x81000d,0x01 },//full defferential mode////////////////////////////////////////////////////////////{0x81008B, 0x01},//I2S 16b It {0x81008d, 0x01},//digital IF3 i2s mode {0x81008f, 0x01},//codec DIF 16bit IIS///////dmic/////////#if (station _id==sbc_station) {0x81001e,0x1b},//ADC1 Digital microphone Connection select£ºdmic1 #elif (station_id==spider_ 
	
	Station) {0x81001f,0x1b},//adc2 Digital microphone Connection select£ºdmic2 #endif//{0x81003c,0x77},//lineout 2=-4db path {0x810079,0x06},//dac1   <= SDTI3 {0x81007a,0x06},//dac2 <= SDTI3 #if (station_id==sbc_station) {0x810075,0x09},//sdto3 <= A DC1 #elif (station_id==spider_station) {0x810075,0x0a},//sdto3 <= ADC2 #endif//power up {0x810003,0x03},//p Ll1&2 Power up {0x810003,0x13},//xtal power up {0x810000,0x01},//power Switch of DSP, SRCA/B/C/D and SRAM blocks { 0x810000,0x03},//logic Reset of DSP, SRCA/B/C/D and SRAM blocks {0x810005,0x05}, {0x810005,0xd5}, {0x810005,0xd7}, {0x 81000a,0x85},//power DAC1 and DAC2 {0x81000b,0x03},//power HP (headphone) {0x81000c,0x33},//power linout 2 {0x81000 F,0X0A},//MPWR2/1C/1B/1A:1V8 {0x810007,0x01},//ain1//{0x810008,0x03},//power ADC1//{0x810008,0x0c},//power ADC 2 {0x810008,0x0f},//power ADC1 and ADC2 {0x810004,0x1f},//};

struct register_element
{
    uint32_t address;
    uint32_t data;

Hal_statustypedef ak4961_reg_mic1_loutr_init (void)
{
	uint8_t i = 0;
	
	for (i = 0; i < (sizeof (CODEC_INIT_MIC1_LOUTR_REG))/(sizeof (struct register_element)); i++)
	{
		if ( Ak4961writereg (codec_init_mic1_loutr_reg[i].address,codec_init_mic1_loutr_reg[i].data)!= HAL_OK)
		{
			return hal_error;
		}
		Delay_ms (a);	
	return HAL_OK;
}

The original can also configure the register, learn