Pseudo-target multi-objective override indicator

In the first example, we mentioned a "clean" target, which is a "pseudo target ",

Clean:
RM *. O temp

Just like "clean" in the previous example, when we generate many file compilation files, we should also provide a "goal" for clearing them for full re-compilation. (Use "make clean" to use this target)

Because we do not generate the "clean" file. "Pseudo-target" is not a file, but a tag. Because "pseudo-target" is not a file, make cannot generate its dependency and decide whether to execute it. Only by explicitly specifying this "target" can we make it take effect. Of course, the name of a "pseudo-target" cannot be the same as that of a file name, otherwise it will lose the meaning of "pseudo-target.

Of course, to avoid duplicate names with files, we can use a special tag ". "Phony" indicates that a target is a "pseudo target" and shows to make that whether or not this file exists is a "pseudo target ".

. Phony: clean

If this Declaration exists, whether or not the "clean" file exists, only make clean is required to run the "clean" object. The entire process can be written as follows:

. Phony: clean
Clean:
RM *. O temp

Generally, the pseudo-target has no dependent files. However, we can also specify the dependent files for the pseudo target. The pseudo-target can also be used as the "Default target", as long as it is placed in the first. For example, if your makefile needs to generate several executable files in one breath, but you just want to simply knock a make file and write all the target files in a makefile, then you can use the "pseudo-target" feature:

ALL: prog1 prog2 prog3
. Phony: All

Prog1: prog1.o utils. o
CC-O prog1 prog1.o utils. o

Prog2: prog2.o
CC-O prog2 prog2.o

Prog3: prog3.o sort. O utils. o
CC-O prog3 prog3.o sort. O utils. o

We know that the first target in makefile will be used as its default target. We declare a "all" pseudo target, which depends on the other three goals. Because the pseudo-target is always executed, the three targets on which it depends are always not as new as the target "all. Therefore, rules for the other three goals will always be determined. In this way, we can generate multiple goals in one breath. ". Phony: All" declares that "all" is a "pseudo target ".

The preceding example shows that the target can also be dependent. Therefore, pseudo targets can also become dependencies. See the following example:

. Phony: cleanall cleanobj cleandiff

Cleanall: cleanobj cleandiff
Rm Program

Cleanobj:
RM *. o

Cleandiff:
RM *. Diff

"Make clean" will clear all files to be cleared. The "cleanobj" and "cleandiff" pseudo targets are a bit like "subprograms. Run the "make cleanall", "Make cleanobj", and "make cleandiff" commands to clear different types of files.

 

 

 

Multi-objective

There can be more than one target in the makefile rule, which supports multiple targets. It is possible that multiple targets depend on one file at the same time, and the generated commands are similar. So we can combine them. Of course, the execution command for Generating Rules for multiple targets is the same, which may cause us trouble, fortunately, we can use an automation variable "$ @" (the automation variable will be described later), which represents the set of all goals in the current rule, this may be very abstract. Let's look at an example.

Bigoutput littleoutput: Text. g
Generate text. G-$ (SUBST output, $ @)> @

The above rules are equivalent:

Bigoutput: Text. g
Generate text. G-big>; bigoutput
Littleoutput: Text. g
Generate text. G-little>; littleoutput

"$" In-$ (SUBST output, $ @) indicates to execute a makefile function. The function name is SUBST, followed by a parameter. The functions will be described later. Here, this function is used to intercept strings. "$ @" indicates the set of targets, just like an array. "$ @" extracts the targets in sequence and runs the commands.

V. Override indicator

If a variable is set by the command line parameter of make, the value of this variable in makefile is ignored. If you want to set the value of this type of parameter in makefile, you can use the "Override" indicator. Its syntax is:

Override <variable >;=< value>;

Override <variable >;:=< value>;

Of course, you can also append:

Override <variable >;+=< more text>;

For variable definitions of multiple rows, we use the define indicator. We can also use the ovveride indicator before the define indicator, for example:

Override define foo
Bar
Endef