PWM output pulse width and frequency (period) settings for the LPC17xx instance

Source: Internet
Author: User
Fin: Crystal Oscillator frequency

M: PLL0CFG [] N: PLL0CFG [] FCCO: PLL output frequency (Phase Lock output frequency) = Fin * 2 * M/N (this is not the case with the calculation formula of S3C2440, for more information, see datasheet)
CCLKSEL []: The frequency division value. Set the frequency division of the CCLK from the PLL0 output signal through the CCLKSEL + 1. CCLK: system clock = FCCO/(CCLKSEL + 1)

PCLKSEL []: Set the PWM1 peripheral clock frequency. All PCLKSEL are two-digit, PCLK = 00: CCLK/: CCLK, 10: CCLK: CCLK/8 PCLK = CCLK/PCLK value (that is, the value of PCLKSEL)

MR0: PWM rate matching register T: PWM cycle = MR0/PCLK

MRn: PWMn output matching register t: PWM pulse width = MRn/PCLK


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