Qsys System Introduction

Qsys is the next-generation product of Sopc Builder.

Qsys System Integration tool automatically generates interconnect logic to connect IP and subsystems

Qsys's design philosophy is to improve the design abstraction level, so that the machine automatically generates the underlying code.

Altera's Avalon Bus IP can be mixed with the arm Amba bus via Qsys.

If a different bus protocol is used, the user can connect the master and slave components by using a bridge element, such as the use of the Amba-ahb-to-avalon bridge.

Qsys component interfaces that can be used by custom components include:

(1) memory-mapped (MM): avalon-mm or Axi primary port and slave port for memory mapping.

(2) Avalon streaming (avalon-st): A point-to-point connection for avalon-st source and homestay.

(3) Interrupts: a point-to-point connection between interrupt senders that generate interrupts and interrupt receivers that perform interrupts.

(4) Clocks, resets: For the clock source, the reset source between the point-to connection.

(5) Conduits: a point-to-point connection between channel interfaces.

(6) Avalon tri-state Conduit: A tri-State bus controller in a qsys system that is used to connect to a tri-state device on a PCB.

Qsys System Introduction