Questions about sampling vsync signals in different clock domains during Video Synchronization

Today, we have debugged the 4 K (3840x1920) vsync signal (clock at 297 MHz) in the 170 MHz clock domain, and found that the output signal jitter is particularly severe. It was later discovered that this was caused by different clock domains. Signals in the fast clock domain may not be collected when entering the slow clock domain. So I change the high level of a clock to the high level of three clocks, so that the slow clock domain can certainly be collected.

Always @ (posedge CLK or negedge reset_n) begin if (~ Reset_n) Begin rdaddr_req <= 1 'b0; // frame_counters <= 13 'b0; end else if (nvsync_dly1 &&(~ Nvsync) Begin rdaddr_req <= 1 'b1; end else if (nvsync_dly3 &&(~ Nvsync_dly2) rdaddr_req <= 1 'b0; // end

Therefore, be careful when handling cross-Clock Domain numbers !!!

Questions about sampling vsync signals in different clock domains during Video Synchronization