"Assembly Instructions" arm instruction set register and 32-bit overview

1)

The ARM processor has a 37+3 32-bit register: 32 General-purpose registers with only one PC pointer register, which is generally used to point to the instruction being taken, rather than the instruction being executed. (Here are the pipelining of ARM processors, described below), seven status registers: But only one CPSR register (to represent the current program State Register), 6 SPSR registers (to hold the exception data that backs up the current program state).

The processor has 8 different operating modes, each of which has a corresponding set of register groups for each processor mode:

Here User/sys work mode is shared with a register group, but user mode has no privileges and no corresponding SPSR register

The current mode of processing determines which set of registers can be manipulated, and which registers can be accessed by any mode.

(1) The corresponding r0~r12

(2) corresponding R13 (SP, stack top pointing) and R14 (LR, link address register, used to record the next time the program will execute the instruction address) and the PC pointer register (generally used to point to the instructions that are being taken by the R15, rather than the instructions being executed)

(3) The corresponding CPSR register (capable of representing the state of the current program the current operating mode of the processor to set some bits of it to change the processor mode and abnormal mode settings as well as the standard bit reflection and settings)

(4) CPSR register when the corresponding exception mode can be accessed in privileged mode

8 operating modes for ARM processors:

The ARM processor performs each instruction in a series of steps: Simple general use of Class 3 pipeline

(1) Take command: Load an instruction from the register

(2) Decoding: Identify the executed instruction, and prepare the data circuit control signal for the next cycle, at this level, the instruction occupies the decoding logic, does not occupy the data path

(3) Execute: Process the instruction and write the result back to the register

CPSR Allocation of register BITS:

where n (negative sign) Z (0 flag) C (Carry flag) V (overflow flag)//where 0~4 bit flag mode is I (IRQ enable bit) F (Fiq enable bit) T (status bit)

N: Negative when n = 1, n = 0 for integer or zero

Control bits:

1) Interrupt Disable bit: when I or F = 1 o'clock, indicates interrupt binary

2) Status control bit: When t = 0 indicates in arm state

3) mode control bit:

MODE (Below is binary)
10000	User mode	Pc,cpsr,r0~r14
10001	FIQ	Pc,cpsr,spsr_fiq,r14_fiq~r8_fiq,r7~r0
10010	Irq	Pc,cpsr,spsr_irq,r14_irq~r13_irq,r12~r0
10011	Management Mode (SVC)	Pc,cpsr,spsr_svc,r14_svc~r13_svc,r12~r0
10111	Termination mode	Pc,cpsr,spsr_abt,r14_abt~r13_abt,r12~r0
11011	Not defined	Pc,cpsr,spsr_und,r14_und~r13_und,r2~r0
11111	System Mode (SYS)	Pc,cpsr,r14 ~r0

"Assembly Instructions" arm instruction set register and 32-bit overview