"Design experience" 1, how to standardize the processing of inout signal

In the FPGA design process, sometimes encounter bidirectional signal (both as output, but also as the input signal is called bidirectional signal). For example, the SDA signal in the IIC bus is a two-way signal, QSPI flash four-wire operation when the four signal lines are two-way signal. Define bidirectional signals in the Verilog with the keyword inout, which summarizes the way the bidirectional signal is processed.

In fact, the nature of the bidirectional signal is composed of a three-state gate, three-state gate can output high level, low and high impedance state three states, in the FPGA, a three-state gate structure as shown:

The Verilog code that describes this logic is as follows:

Module inout_top (input       i_data_in        ,inout       io_data          ,  Output     o_data_out     ,input       Control); Assign 1 ' BZ; Assign O_data_out = io_data;    

When control is 1 o'clock, io_data is output, output i_data_in value

When control is 0 o'clock, io_data is input and the input signal is assigned to O_data_out

This code is shown in the RTL diagram in the Vivado2015.4.2 compilation environment

The RTL diagram in ISE14.7 's compiled environment is shown

Can be found in the Vivado2015.4.2 environment control signal ibuf behind incredibly also integrated out a lut, in the ISE14.7 environment control signal after the synthesis of a reverse device, the reason for this lut and reverse is the control of 1 to the IO _data is set to output, while in Xilinx a iobuf resource default T-end is 0 o'clock IO end is output, T end is 1 o'clock, Io end is input, so the

Assign Io_data = Control? I_data_in:1 ' BZ;

Switch

Assign Io_data = (Control = = 1 ' b0)? I_data_in:1 ' BZ;

The RTL diagram integrated in the Vivado2015.4.2 environment is

The RTL diagram that is integrated in the ISE14.7 environment is shown

Obviously, the inverter in the Lut and ISE environments in the Vivado environment is missing, saving 1 cell resources.

The above is the first method to deal with InOut, the second way to process the inout signal is to call Xilinx iobuf Primitive, iobuf primitive can be found in Vivado2015.4.2 language

The Verilog code that invokes this primitive is as follows:

ModuleInout_top (inputi_data_in,inoutIo_data,OutputO_data_out,inputControl); IOBUF # (. Drive ( A),//Specify the output drive strength. IBUF_LOW_PWR ("TRUE"),//Low Power-' TRUE ', high performance = ' FALSE '  . Iostandard ("DEFAULT"),//Specify the I/O standard. SLEW ("SLOW")//Specify the output slew rate) Iobuf_inst (. O (o_data_out),//Buffer Output. IO (Io_data),//Buffer inout Port (connect directly to top-level port)  . I (i_data_in),//Buffer Input. T (Control)//3-state Enable input, High=input, Low=output);Endmodule

The RTL diagram integrated in the Vivado2015.4.2 environment is shown

The RTL diagram integrated in the ISE14.7 environment is shown

Obviously and assign Io_data = (Control = = 1 ' b0)? I_data_in:1 ' BZ; In this case the RTL is exactly the same.

In summary, there are two ways to process bi-directional signals using Verilog:

1. Write code

Assign Io_data = (Control = = 1 ' b0)? I_data_in:1 ' BZ;

Assign o_data_out = Io_data;

2, the case of IOBUF primitive language

IOBUF # (

. Drive (+),//Specify the output drive strength

. IBUF_LOW_PWR ("true"),//Low Power-"true", high performance = "FALSE"

. Iostandard ("DEFAULT"),//Specify the I/O Standard

. SLEW ("SLOW")//Specify the output SLEW rate

) Iobuf_inst (

. O (O_data_out),//Buffer output

. IO (Io_data),//Buffer inout port (connect directly to top-level port)

. I (i_data_in),//Buffer input

. T (Control)//3-state enable input, High=input, low=output

);

Off Topic:

Recently tuned a set of code, the code is written by the predecessor, before is developed with Ise, the set of code with ISE compiled bit files can run normally, but the latest project because to add more features, so the K7 series of FPGA, developed under Vivado, The results found that the original normal operation of the code in Vivado can not be run, through repeated inspection and positioning, found that the original set of code on the InOut signal processing is very irregular, and there is no control this signal to control the direction of InOut, To use as input or output directly. Finally, we use the above two specifications of the InOut signal processing method after processing, code normal operation. So usually in the process of design must pay more attention to detail, and strive to standardize.

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"Design experience" 1, how to standardize the processing of inout signal