"FPGA full Step---Practical Walkthrough" the fourth chapter of Quartus II use tips

Tip 1: "New" skill hierarchies warning to find

After compiling, the word "hierarchies" in the warning is familiar to everyone, and seeing this warning is basically the problem that occurs when the case is instantiated. In general, if a connection does not come up, is not connected, or is a bit wide mismatch will be out of this warning. And we usually locate the sample file, or observe the RTL view to look for, but the project is not so easy to find a big ah!

Warning:1 hierarchies has connectivity warnings-see the Connectivity Checks Report folder

Here's how to fix it:

Click the icon in Figure 6.1 and find the connectivity checks,6.2 shown in the analysis & Synthesis file, and click to see where the problem occurs when the description is instantiated.

Figure 6.1 Operation (i)

Figure 6.2 Operation (ii)

Tip 2: Bit width mismatch

When many of the Reg variables are assigned, they often encounter a bit-width mismatch, as shown in 6.3. The number in the front bracket represents the row label in the program, stating that the assignment is 32 bits wide and is assigned a 1-bit width, which is to truncate the 32-bit width to match the 1-bit width. If you know in the program that it is indeed an assignment, the reg type variable is a one-pass, so you can not follow this warning, the program shown in 6.4. You can see that you really need to assign a value in the Reg variable. If you want to eliminate this warning, you can use the modification program shown in Figure 6.5. 0 will be changed to 1 ' B0, quartus if the variable is not assigned to the number of digits, 32-bit processing. The compiled results are shown in 6.6.

Figure 6.3 Bit width mismatch

Figure 6.4 Source Program

Figure 6.5 The modified program

Figure 6.6 Post-compilation results

Tips for using 3:TCL files

In the pin assignment, often for a vast project, the number of pins is many, if one to allocate, time-consuming and laborious, waste, in fact, can use TCL files, just change a few signal instructions can be. As shown in Fig. 6.7, the callout in the figure is changed to the name of the signal used in the module. Figure 6.8 is the operation of Quartus II, click on TCL scripts, and then click on the position shown in Figure 6.9, you can. Figure 6.10 is the distribution of the Pin planner.

Figure 6.7 Tcl File

Figure 6.8 Operation in Quartus II (i)

Figure 6.9 operation in Quartus II (II)

Figure 6.10 Pin Planner Assignment

Tips for 4:jic Curing file generation

Click File----Convert programming file, and the interface shown in 6.11 appears. Select the. JIC in the programming file type, select the EPCS4 in the configuration device (this is based on the selection of the chip's profile that you use, the author is EPCS4), and then select the Flash loader in Figure 6.12 , click Device, then select the device type, the EP3C5 chip is designed by the author. When you select SOF data, the SOF file is loaded, and clicking Generate appears to generate a successful interface. Then open the output files in the project directory to see the generated JIC file, as shown in 6.14. Then go to the programming download interface, 6.15, click Add File, the Jic file just generated to load, 6.16, the original SOF file is deleted, and select Program/configure, click Start, and then re-electric observation effect.

Figure 6.11 Configuration Interface (i)

Figure 6.12 Configuration Interface (ii)

Figure 6.13 Configuration Interface (iii)

Figure 6.14 the generated JIC file

Figure 6.15 Download interface

Figure 6.16 Adding a Jic file

"FPGA full Step---Practical Walkthrough" the fourth chapter of Quartus II use tips