"OPENHW12" zedboard-custom IP Core Implementation +ps successful call "detailed steps + Process introduction + source" Reprint

Article source

Images cannot be copied, please see the original

Http://www.eefocus.com/jefby1990/blog/13-03/291975_490bc.html

"OPENHW12" zedboard-custom IP Core Implementation +ps successful call "detailed steps + Process introduction + source" 2013-03-07 17:56:30 share:

(Please click to view the original picture)

Software Environment: Win7_64 + ISE 14.4 (system_edition)

Hardware: Zedboard, usb-cable Line

Construction diagram:

After a few days of study, check the data sheet, the official routine, the author has a basic understanding of zedboard, but how to give full play to the advantages of ZYNQ? This will have to say ZYNQ basic architecture, it is divided into PS (processing System) and PL (Programmable Logic) two parts. PS integrates dual-core arm cortex-a9 with many common peripherals such as DDR Controller, USB controller, and various common bus interfaces. PL section: Zedboard uses Xilinx chip xc7z020, and viewing official data shows that it uses the same architecture as the 7 Series Aritex, which is incredibly powerful! To maximize the performance of the ZYNQ chip, you can combine the PS and PL sections, and this first needs to know how to customize the generic IP core, import it into PS, and then write drivers and applications to get started. I just started also confused, check Help, the official tutorial, but most of the information is just how to use the ISE provided by the off-the-shelf IP core, for how to define the user's own IP core is either not say or talk is very vague, the author personally toss more than 10 times before finally understand, the detailed process is now recorded as follows , so that later people can take less detours.

After the author personally try to customize the IP core and use in PS in the approximate process 1 is shown.

Figure 1

The author of this project is based on the Zedboard Development Board, the function of the IP core is to read the state of the dial switch, and write data control LED lights. The application outputs the status of the dial switch on the output table and writes the 0x24 to the LED light. Here's how:

1, open Planahead to create a new project, and configure the XPS (slightly), not clear can refer to the author's written previous blog post, http://www.eefocus.com/jefby1990/blog/13-03/291863_e5055.html

2, when the Planahead default open XPS, 2, adjust the parameters to make 3, because we want to define their own IP core to use LED and SW, so delete the corresponding IP core, the other button is useless, it can also be deleted.

Figure 2

Figure 3

3. Click Finish. At this time, about a minute or so in the XPS appeared in the Zynq of the Sav diagram, at this time, click on the black rectangle in Figure 4, create or import peripherals, followed by the default click Next, until Figure 5, create and configure their own IP core in Figure 5, and then next,6, select Axi4-lite Bus , Axi full name is advanced extensive Interface, is the next important bus interface of AMBA, and Axi-lite is a lite version of the Axi Bus protocol, the details can refer to Xilinx help documentation. Click next,7, this is Xilinx to simplify the user workload between the IP and the Axi bus function module Ipif, and then continue to next,8 as shown, at this time set the number of user read and write registers is 2, because we need to read the status of the dial switch SW, and use data control LED lights , so two registers are required. next,9, keep the default, do not modify, and then all the way next to Figure 10, generate Ise project files and drivers, the first option can also not choose, I am more familiar with VHDL, it is not selected, familiar with Verilog can hook on, then next, click Finish. At this point, we can see the IP core My_gpio we created in the XPS IP catalog. As shown in 11.

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

The next step is to modify our IP core so that it meets our requirements, at this point, open the Planahead project directory, locate the generated My_gpio Ise project file, 12, Continue to open the Project3.srcs folder, open the subfolder by path until the ISE project file appears, 13,  use Ise to open the file, and open the file user_logic. As shown in the VHD file 14, add two lines of code as shown in the Red rectangle section. This is the IP port that we have defined for ourselves. View User_logic. The VHD code knows that two registers are slv_reg0 and SLV_REG1, and we use SLV_REG0 as data registers for the SW and Axi buses, then the register is read-only, and for that, comment out the register-write logic, as shown in 15, next define our own signals Sw_ REG0,SW_REG1, (in order to synchronize the SW signal) 16, continue to add the synchronization logic, 17, the next step, add write LEDs and read the SW state logic, as shown in method 18, and then change the top-level file My_ GPIO.VHD, in the code shown in Figure 19, add Port 20, and then 21 to add code in the User_logic_i module, so after the IP logic is basically finished, use the integrated tool to synthesize and view the RTL view, 22 and 23, As can be seen from Figure 23, we define the port led and SW are effectively defined, the next step, back to XPS, 24 to view the MPD file, MPD (microprocessor peripheral definition), the microprocessor peripheral definition file, and 24 add code and save, then, 25 operation, Rescan user repositories, re-scan users directory, immediately after, add the design of the IP core, 26 is shown  , the following default, and finally 27, you can see that our added interface has been shown, The next step is to get our ports out, as shown in Figure 28 and 29, and finally 30, the next step is to assign our peripherals mapped to memory addresses, GP0 and GP1 are common I/O ports, GP0 range is 0x4000000~0x7fffffff, The scope of the GP1 is shown in 0x80000000~0xbfffffff,31, we can see that the system has set the default address 0x75c00000~0x75c0ffff for us, just lock it. Click Graphic Design view to see the port of the IP core we designed. As shown in 32. Next, turn off XPS, go back to Planahead, right-click System to add top HDL files for this design, as shown in 33,

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Figure 31

Figure 32

Figure 33

Then, 34 shows the operation, add a file, pop-up window, 35 make a selection, then next,36 the action, and determine, generate the constraint file, then, Open the generated SYSTEM.UCF file, edit 37 as shown, last save, and 38, click on the area shown in the red rectangle to generate a bit stream file, complete with 39. Then, 40, export the hardware to the SDK,

Figure 34

Figure 35

Figure 36

Figure 37

Figure 38

Figure 39

Figure 40

41, set, click OK, then. Inside the SDK, My_gpio address Map 42, we create a new project, 43 shows, and 44 set the project, click Next, select Memory Test,finish. Then 45, click on the shaded area shown, and remove the automatic compilation option. Then go to directory E:\Project\openhw\project_3\project_3.srcs\sources_1\edk\system\drivers\my_gpio_v1_00_a\src to find the file My_ GPIO.C and my_gpio.h, and copy it to the directory E:\Project\openhw\project_3\project_3.sdk\SDK\SDK_Export\my_gpio\src, and then we open the My_ Gpio.h and MY_GPIO.C can see that this is the encapsulation of functions Xil_out32 and Xil_in32, as shown in 47,

Figure 41

Figure 42

Figure 43

Figure 44

Figure 45

Figure 46

Figure 47

We modified the file memory_test.c as shown below,

#include <stdio.h>

#include "Xparameters.h"

#include "Xil_types.h"

#include "Xstatus.h"

#include "xil_testmem.h"

#include "platform.h"

#include "Memory_config.h"

#include "my_gpio.h"

#define BASE_ADDR 0x75c00000

int main ()

{

unsigned int i;

Init_platform ();

Read the SW state, this function is a driver that Xilinx wrote for us, included in the header file My_gpio.h

i = My_gpio_mreadreg (base_addr,0);

xil_printf ("SW state is%x", i);

Write 0x24 to LED light

My_gpio_mwritereg (base_addr,0x00000004,0x24);

Cleanup_platform ();

return 0;

}

Figure 48

Finally, compile the project, after the completion of the power supply, the bit down to the FPGA Development Board, configure the serial port, run, (not clear can go to see my previous post http://www.eefocus.com/jefby1990/blog/13-03/291863_ E5055.html, there are detailed steps), and then press 49 to configure the operating environment, click OK, then 50, click the Red rectangle button, generate debug, and run it! The serial output results in 51. The switch status and led condition 52 are shown. That runs successfully! is not a very fulfilling feeling ah!

Figure 49

Figure 50

Figure 51

Figure 52

Finally, I want to say that this is just a start, no interruption, high-level calls, etc., but we have a general understanding of the basic process, the rest is the problem of perfect function. In addition, due to the author's limited level, have any questions please point out (by message or email contact)! Thank you!

This is a PDF version of the original project and Ben Boven (personal recommended download). Need to be able to download! Pan.baidu.com/share/link

Jefby.

[Email protected]

"OPENHW12" zedboard-custom IP Core Implementation +ps successful call "detailed steps + Process introduction + source" Reprint