"Repost" Cortex series m0-4 simple contrast

Reprint website: http://blog.sina.com.cn/s/blog_7dbd9c0e01018e4l.html

Recently engaged in a block of St's CORTEX-M4 processor, and then down this document. Share a bit.

In view of the current into the public vision of M0, M3, M4 made the following simple comparison, the content from arm and other official website, here is just finishing the next, looks more intuitive point, hehe.

The CORTEX-M series is optimized for mixed-signal devices for cost and power-sensitive MCU and end-use applications such as smart measurement, man-machine interface equipment, automotive and industrial control systems, large household appliances, consumer products and medical devices.

First, compare Cortex-m processor

The CORTEX-M series processors are binary-up compatible, which makes it possible to reuse software and seamlessly evolve from one cortex-m processor to another.

M cortex-m Technology

CMSIS

The ARM Cortex microcontroller software Interface Standard (CMSIS) is a vendor-independent hardware abstraction layer for the Cortex-m processor family. With CMSIS, you can implement a consistent and simple software interface for interface peripherals, real-time operating systems, and middleware, simplifying software reuse, shortening the learning process for new microcontroller developers, and reducing time to market.

In-depth: nested vector interrupt Controller (NVIC)

The NVIC is an integral part of the CORTEX-M processor, which provides excellent interrupt handling capabilities for the processor.

The CORTEX-M processor uses a vector table that contains the address of the function to be executed for a particular interrupt handler. When an interrupt is accepted, the processor extracts the address from the vector table.

To reduce the number of gates and enhance system flexibility, the CORTEX-M processor uses a stack-based exception model. When an exception occurs, the system pushes critical general-purpose registers onto the stack. After completion of the stack and instruction extraction, an interrupt service routine or a fault handler is executed, and the registers are automatically restored for the interrupted program to resume normal execution. With this approach, you do not have to write assembler wrappers (which is necessary for performing stack operations on traditional C-based interrupt service routines), making application development very easy. NVIC supports interrupt nesting (into the stack), allowing the service of an outage to be served earlier by applying a higher priority.

Complete the response to interrupts in the hardware

The interrupt response of the CORTEX-M series processor is the number of cycles from the time the interrupt signal is signaled to the execution of the interrupt service routine. It includes:

• Detect interrupts
• Optimal handling of back-to-rear or late interrupts (see below)
• Extracting vector addresses
• Stack easily damaged registers
• Jump to interrupt Handler

These tasks are performed in hardware and are included in the interrupt response cycle time that is reported for the CORTEX-M processor. In many other architectures, these tasks must be executed in the software's interrupt handlers, causing delays and making the process complex.

Tail chain in the NVIC

In the case of an off-back interruption, the traditional system repeats the complete state save and restore cycle two times, resulting in higher latencies. The CORTEX-M processor simplifies the transition between active interrupts and suspended interrupts by implementing tail-chain technology in the NVIC hardware. The processor state is automatically saved on the interrupt entry and restored at interrupt exit during periods that are less than the software implementation time, significantly improving the performance of the low MHz system.

NVIC response to higher-priority interrupts that are late

If you are late for a higher-priority interrupt during a stack push for the previous interrupt, NVIC immediately extracts the new vector address to service the pending interrupt, as shown above. Cortex-m NVIC provides a deterministic response to these possibilities and supports lateness and preemption.

NVIC the Stack popup preemption

Similarly, if an exception arrives, NVIC discards the stack popup and immediately serves the new interrupt as shown above. by preemption and switching to a second interrupt without completing the state restore and save, the NVIC achieves a shortened delay in a deterministic manner.

Second, why Choose

1. Why Choose CORTEX-M0

Smallest ARM processor with the lowest energy consumption

CORTEX-M0 's code density and energy efficiency benefits mean that it is the natural cost-effective replacement for 8/16-bit devices in a variety of applications, while preserving the tools and binary upward compatibility with the feature-rich CORTEX-M3 processor.

Ultra-low energy consumption

The CORTEX-M0 processor consumes only 85µw/mhz (0.085 MW) in an area less than a K-gate, leveraging unparalleled ARM expertise as a leader in low-energy technologies and a key player in creating ultra-low-power devices.

Simple

There are only 56 instructions, so you can quickly master the entire CORTEX-M0 instruction set (if needed), but its C-friendly architecture means it is not required. The choice of fully deterministic instruction and interrupt timing makes it easy to calculate response times.

Optimized connectivity

Designed to support low-power connections, such as Bluetooth Lower Energy (BLE), IEEE 802.15, and z-wave, especially in such analog devices: these analog devices are increasing their digital capabilities to efficiently preprocess and transfer data.

2. Why Choose CORTEX-M3

delivers higher performance and richer functionality

Introduced in 2004, recently updated with new technology and updated with CORTEX-M3, is a major ARM processor developed specifically for microcontroller applications.

Performance and energy efficiency

With high performance and low dynamic energy consumption, the CORTEX-M3 processor delivers the leading benefits: 12.5 DMIPS/MW on a 90nmG basis. Combining the integrated sleep mode with the optional state Retention feature, the CORTEX-M3 processor ensures that there is no tradeoff for applications that require both low power consumption and excellent performance.

Full function

The processor executes the thumb®-2 instruction set for optimal performance and code size, including hardware division, single-cycle multiplication, and bit field operations. The CORTEX-M3 NVIC is highly configurable at design time and provides up to 240 system interrupts with individual priority, dynamic reset priority, and integrated system clocks.

A rich connection

The combination of functionality and performance enables CORTEX-M3-based devices to efficiently handle multiple I/O channels and protocol standards, such as USB OTG (on-the-go).

3. Why Choose CORTEX-M4

Target use: Flexible solutions for the emerging categories of motor control, automotive, power management, embedded audio and industrial automation markets.

Award-winning high-efficiency digital signal control

CORTEX-M4 offers unparalleled capabilities to integrate 32-bit control with leading digital signal processing technologies to meet the market where high energy efficiency is required.

Easy-to-use technology

CORTEX-M4 makes it easy to develop signal processing algorithms with a range of excellent software tools and Cortex microcontroller software Interface Standards (CMSIS).

Third, the specification

1, M0

The ARM CORTEX-M0 processor executes the Thumb instruction set, including a small number of 32-bit instructions that use Thumb-2 technology. This is a binary up compatible subset of the instruction set supported by ARM CORTEX-M3 and arm cortex-m4.

2, M3

The core area, frequency range, and power consumption depend on the process, library, and optimization. The numbers quoted above are a description of the synthesis core using the generic TSMC process technology and ARM physical IP standard cell library and RAM. Area figures include Cm3core, nested vector interrupt controllers (NVIC), and bus matrices, but do not include optional components (including memory protection Unit, embedded Tracking Macro unit, breakpoint unit, data detection point unit, and Trace port Interface unit).

The implementation of speed optimization refers to the choice of library, synthesis flow decision and tradeoff in order to achieve the target frequency performance. The implementation of area optimization refers to the choice of library, composition flow decision and tradeoff in order to achieve the target area density.

3, M4

The core area, frequency range, and power consumption depend on the process, library, and optimization. The numbers quoted above are a description of the composite cores using low-power process technology and ARM physical IP standard cell libraries and RAM. Area figures include the central kernel (including DSP extensions, nested vector interrupt controllers (NVIC), and bus matrices), but do not include optional components (including memory protection Unit, embedded Tracking Macro unit, breakpoint unit, data detection Point unit, and Trace Port Interface unit.

The implementation of speed optimization refers to the choice of library, synthesis flow decision and tradeoff in order to achieve the target frequency performance. The implementation of area optimization refers to the choice of library, composition flow decision and tradeoff in order to achieve the target area density.

The following point is a M4 page-specific introduction:

System IP

System IP components are critical to building complex systems on the chip, and by leveraging system IP components, developers can significantly shorten development and validation cycles, saving costs and reducing time-to-market for products.

Note: The above content is excerpted from http://www.arm.com/

At present, some mainstream manufacturers of product introduction:

Texas Instruments:

1. LM3SXXXX Series (M3)
2. LM4FXXXX Series (M4)

STMicroelectronics:

1. STM32 f0xx Series (M0 48MHZ)
2. STM32 lxxx Series (M3 32MHZ)
3. STM32 f1xx Series (M3 72MHZ)
4. STM32 f2xx Series (M3 120MHZ)
5. STM32 f4xx Series (M4 168MHZ)

NXP:

1. LPC11XX lpc12xx Series (M0)
2. LPC13XX lpc17xx lpc18xx Series (M3)
3. LPC43XX Series (M4)

Freescale:

1. Kinetis L Series (m0+)
2. Kinetis x series, K series (M4)

Atmel:

1. sam3s/u/n Series (M3)
2. SAM4S Series (M4)
3. SAM7XXXX Series (ARM7)
4. SAM9XXXX Series (ARM9)

Infineon:

1. XCM4000 Series (M4, the first MCU for Infineon to launch arm architectures)

"Repost" Cortex series m0-4 simple contrast