"Self-made CPU Learning Chapter 06" Register

The previous article learned the relevant knowledge of the bus, on the way ABC was assumed to be a 8-bit register. This article will learn how to build this register .

　　　　

This is divided into two three parts, data input, register, data output. First of all, regardless of the output, look at the data input and register two parts. "03 Trigger and Latch" in the D-type trigger, then our register (d register) is composed of D latch (74ls74), the structure is as follows:

　　　　

A 2-bit register is drawn in the figure, and each part is a 1-bit register, and 8 such 1-bit registers are required if the total is 8 bits. The load side is 0, so the output Q will not change regardless of the data end. If the load side is 1, when the clock is on the edge, Q will save D incoming data. The above register takes a load of 0 for example, and the following is the load of 1. The actual figure is as follows:

　　　　

The median four digital circuits are 74ls04 (inverter), 74ls08 (with gate), 74LS32 (or gate), 74ls74 (type D latch). The Yellow line is load, the blue line is data, the white line is the clock CLK, and can be connected to a PC previously made with 555 timers. The experiment can then connect the Yellow line to + or-, indicating load to 0 and 1. This is where you will see the light bulb (the data of the Register), which, along with CLK, will store or ignore the value of the Blue line data according to the value of the load.

The input and storage of such a 1-bit register is done and the output is not. Blue Line only need to access the bus, you can receive data from the bus, but the data output to the bus, need to do some processing, need to connect a tri-state bidirectional bus transceiver. This is in the "05 Bus" in this article has been told why.

　　Integration : So far we've learned that a 1-bit register is made from input to output, and 8 bits requires 8 of these combinations. Here we can directly use two 4bit D-type registers with 3-state outputs (74ls173). As the name implies, the 3-state output of the 4-bit D-Register IC. Here to explain, although we have to do the CPU, but easy to change convenience. We certainly can not be convenient to directly with a 8086 on the bread board even if a CPU, but of course, can not use the basic gate circuit, even with two transistors and capacitors to do the CPU, we have to find a compromise to approach, in understanding the principle, but the repetition of the higher parts, as far as possible to use the. Bit 74ls173 pin Graph:

　　　　

• CP Clock input (up-edge active)
• CR Clear End
• 1~4D Data Input Terminal
• 1~4q Output Terminal
• N,m three-state allow (active low)--output to Bus
• G1,G2 Data-selectable end (active low)--whether to deposit

The official note is introduced here:

　　

This allows the two 74ls173 to form a 8-bit register that includes control of the input and output terminals. Since the CPU in practice is designed to visually see the contents of the registers, we want to be able to observe the contents of the registers with LEDs regardless of the control signal output to the bus. So we make 74ls173 output control is always output, connected to the LED light, and then a 74ls245 (tri-State control) to control whether the signal output to the bus. The design diagram is as follows:

　　　　

Where the m,n is always grounded, that is, the low level is effective, the output has been effective, through the LED lights and then three-state output processing.

The first step of the actual diagram:

　　　　

Practical diagram The second step: The register output is connected to the three state, the output of the tri-State is connected to the bus. The bus is also connected to the register through the Blue Line to the input, there are three yellow lines, the far right is load (whether the data is deposited), the middle is clear (forever 0), the left is the three-state permission (whether output to the bus). The white line is CLK.

　　　　

Connect the device to the PC and the bus:

　　　　

To connect multiple registers:

　　　　

　　Summary : At this point multiple registers have been able to interact with the bus, and connected to the PC, with the clock to change, through load and tri-state determine whether to load and output data.

　　Reference Video : eater.net