"Self-written operating system" Chapter III PMTEST9 Source parsing-Interrupt Handler

In this section, we will learn an important feature of modern operating systems-the interrupt handling mechanism. In the same way, the interrupt processing is also the hardware and software co-operation, in which part: 8259A is responsible for the programmable interrupt controller, through the read-write port, to achieve interrupt signal and interrupt number of the binding, etc. the CPU through the gate descriptor and interrupt vector table to implement the interrupt service program. Finally, the process of accessing an interrupt and accessing a door is similar, and the reader can make a corresponding comparison. This article, mainly through Pmtest9 explain the writing of interrupt program.

the implementation of the interrupt gate includes the following: Setting up 8259A, interrupting the reading and writing of hardware information, establishing IDT, and implementing an interrupt.

1. PreviewIn protected mode, the interrupt mechanism has changed a lot. The interrupt vector table is replaced by IDT and is not available in the BIOS interrupt protection mode that can be used in real mode. IDT, the interrupt descriptor, contains interrupts, traps, and task gates that correspond to each interrupt vector and descriptor. The descriptor for the interrupt gate and Trap Gate is as follows:

The corresponding process from the interrupt vector to the interrupt handler: the

invocation gate is similar to the interrupt processing mechanism, but the former uses the call instruction, the latter with the INT directive. In addition, the task gate is not used in Linux, so we don't have to do too much explaining.

2. Interrupts and exception mechanismsTwo basic questions: what kind of interrupts can a processor have? Receive interrupts how to process. The description of interrupts and exceptions in protected mode can be found here:

Exceptions and interrupts
in protected mode

2.1 For exceptions

Pay attention to the difference and connection between fault, TRAP and abort.

2.2 for interruptsExternal interrupts need to establish a connection between the interrupt and the vector number. External interrupts are divided into non-shielded interrupts and can be shielded from interrupts, which are received by the CPU's NMI and INTR, respectively. The structure is as follows: The relationship between the masked interrupt and the CPU is achieved by setting the programmable Interrupt controller. So how does the interrupt request correspond to the interrupt vector? When the BIOS is initialized, IR0~IR7 is set to the corresponding vector 08h~0fh, and through the table, we know that the vector number 08H~0FH in protected mode is already occupied, we can only set the new 8259A, this can be by writing to a specific port ICW (initialzation Command Word) to implement. 3. Programming Operation 8259A 3.1 What is a port

A port is a number of registers in an interface circuit that are used to hold data information, control information, and status information, respectively, and the corresponding ports are called data ports, control ports, and status ports.

Computer running System program, in fact, like a closed circle, but the computer is for human service, he needs to accept some instructions, and to follow the instructions to adjust the system function to work, so the System program designer, the circle cut into a lot of segments, these line interface is called the port (colloquially is the fracture, is interrupted), When the system runs to these ports, a look at whether the port is turned on or off, if it is closed, the rope is connected, the system runs down, if the port is open, the system will get commands, external data input, accept external data and execute.

Where the main 8259A and the corresponding port address from 8259A are 20h/21h and a0h/a1h.

the format and meaning of 3.2ICW

Related code:

;
init8259a--------------------------------------------------------------------------------------------- Init8259a:mov al, 011h out 020h, AL;
    Lord 8259, ICW1. Call Io_delay out 0a0h, AL;
    From 8259, ICW1. Call Io_delay mov al, 020h; IRQ0 corresponding interrupt vector 0x20 out 021h, AL;
    Lord 8259, ICW2. Call Io_delay mov al, 028h; IRQ8 corresponds to interrupt vector 0x28 out 0a1h, AL;
    From 8259, ICW2. Call Io_delay mov al, 004h; IR2 should be 8259 out 021h, AL;
    Lord 8259, ICW3. Call Io_delay mov al, 002h; Corresponding to the main 8259 IR2 out 0a1h, AL;
    From 8259, ICW3. Call Io_delay mov al, 001h out 021h, AL;
    Lord 8259, ICW4. Call Io_delay out 0a1h, AL;
    From 8259, ICW4. Call Io_delay mov al, 11111110b; Just turn on the timer interrupt; Mov al, 11111111b; Shield Master 8259 all interrupts out 021h, AL;
    Lord 8259, OCW1. Call Io_delay mov al, 11111111b; Shielded from 8259 all interrupts out 0a1h, AL;
    From 8259, OCW1. Call Io_delay ret; init8259a ---------------------------------------------------------------------------------------------
 

The above code consists of two parts: The settings section of the interrupt vector + the settings section of the interrupt mask. The setting of the shield is done by OCW. OCW: is Operation Control Word, OCW1 is used to set the masking information, OCW2 is used to send the EOI signal (end of int), which means that interrupt processing is complete and the next interrupt can be accepted. The OCW settings are implemented by 21h and a1h, with the following structural meanings:

4. Establish IDTThis step and set the GDT class; After IDT initializes, it is not possible to return to real mode from protected mode because the contents of IDTR and 8259A have been changed. Notice the changes before and after the IDTR. 5. Clock Interrupt ExperimentHere, we will turn on the clock interrupt IRQ0. Modify the code that initializes the 8259A to enable IRQ0; set IDT; Bind interrupt handler function. Turn on clock interrupt: mov al, 11111110b; Just turn on the timer interrupt

Set IDT:

; IDT
[section. IDT]
ALIGN
[BITS   ]
Label_idt:
; gate                                target selector,            offset, DCount, properties
%rep
            Gate    SelectorCode32, Spurioushandler,      0, da_386igate
%endrep
. 020h:          Gate    SelectorCode32,    Clockhandler,      0, Da_386igate
%rep-up
            Gate    SelectorCode32, Spurioushandler,      0, da_386igate
%endrep
. 080h:          Gate    SelectorCode32,  Userinthandler,      0, da_386igate

idtlen      equ $-Label_idt
idtptr      DW  IdtLen-1  ; segment boundary
        dd  0       ; base address
; END of [section. IDT]

To bind the interrupt handler function:

; int handler---------------------------------------------------------------
_clockhandler:
Clockhandler    equ _clockhandler-$$
    inc Byte [GS: ((0 +) * 2)]   ; screen No. 0, column 70th.
    mov al, 20h out
    20h, Al             ; send EOI
    iretd

Binding:

    mov al, 020h    ; IRQ0 corresponds to interrupt vector 0x20 out
    021h, Al    ; main 8259, ICW2.
    Call    Io_delay

Open Interrupt:

int 080h
    xchg    bx,bx
    sti
    jmp $

6. OtherThere are eflags (and error code) that need to be in the stack compared to the interrupt gate and the call gate, and the stack switch is as follows (there may be a privileged switch): It changes the eflags from an interrupt or an exception return to use IRETD, compared to Ret. In addition, when IRETD executes, error code does not automatically eject from the stack and needs to be cleared manually. The difference between an interrupt gate and a trap gate is that the interrupt generated by the trap gate does not change if.