"stm32f407" window watchdog Wwdog

A. Window Guard Dog

Window watchdog (WWDG) is often used to monitor software failures caused by external interference or unforeseen logic conditions that result from an application deviating from a normal running sequence. Unless the value of the decrement counter is refreshed before the T6 bit (sixth bit of WWDG->CR) becomes 0, the watchdog circuit generates an MCU reset when it reaches the preset time period. Before the decrement counter reaches the window configuration register (WWDG->CFR) value, if the 7-bit decrement counter value (in the control register) is flushed, an MCU reset is also generated. This indicates that the decrement counter needs to be refreshed in a limited time window. As shown in figure:

T[6:0] is WWDG_CR low seven bits, w[6:0] that is WWDG->CFR low seven bits. T[6:0]

Is the window watchdog counter, while w[6:0] is the window watchdog's upper window, the bottom window value is fixed (0X40). A reset occurs when the window watchdog's counter is refreshed outside the upper window value, or below the lower window value. The upper window value (w[6:0]) is set by the user himself, according to the actual requirements to design the window value, but make sure that the window value is greater than 0x40, otherwise the window will not exist.

The timeout formula for window watchdog is as follows:

Twwdg= (4096X2^WDGTBX (t[5:0]+1))/fpclk1;

which

TWWDG:WWDG time-out (in MS)

FPCLK1:APB1 clock frequency (in khz)

The prescaler coefficient of WDGTB:WWDG

T[5:0]: Window watchdog counter low 6 bits

According to the above formula, assuming Fpclk1=42mhz, then you can get the minimum-maximum timeout schedule as shown in the figure:

Next, we introduce the 3 registers of the window watchdog. First introduce the control register (WWDG_CR), the register of the description as shown in figure

As can be seen, here our WWDG_CR only low eight bit effective, t[6:0] used to store the watchdog counter value, updated at any time, each window watchdog Count cycle (4096X2^WDGTB) minus 1. When the value of this counter changes from 0x40 to 0x3f, a watchdog reset is generated. The WDGA bit is the watchdog activation bit, which is set by the software 1 to start the watchdog, and it is important to note that once the bit is configured, it can only be zeroed after the hardware reset.

The second register of the window watchdog is the configuration register (WWDG_CFR), and the registers are described in the figure

The EWI in this bit is an early wakeup interrupt, that is, a period of time before the reset is imminent (t[6:0]=0x40) to remind us that we need to feed the dog, otherwise it will be reset. Therefore, we generally use this bit to set the interrupt, when the window watchdog counter value is reduced to 0x40, if the bit is set, and the interrupt is turned on, there will be an interrupt, we can in the interrupt to WWDG_CR to write the counter value, to feed the dog's purpose. Note that after entering the interrupt, the WWDG_CR must be re-written within the time of the watchdog count period of no more than 1 windows (in the case of a PCLK1 frequency of 42M and a WDGTB of 0, the time is 97.52us), otherwise the watchdog will produce a reset.

Finally, we are going to introduce the status register (WWDG_SR), which is used to record whether there is a sign of early wakeup. This register only has bit 0 valid, others are reserved bits. When the counter value reaches 40h, this bit is set by hardware 1. It must be cleared by software write. Write 1 for this bit is not valid. Even if the interrupt is not enabled, when the counter value reaches 0x40, this bit will also be set to 1, window watchdog library function related source code and definition distributed in the file Stm32f4xx_wwdg.c file and header file Stm32f4xx_wwdg.h two. Windows watchdog app

1) Enable WWDG clock

The WWDG differs from the IWDG,IWDG having its own independent 32Khz clock, which does not exist to enable the problem. While WWDG is using the PCLK1 clock, the clock needs to be enabled first. The method is:

Rcc_apb1periphclockcmd (RCC_APB1PERIPH_WWDG, ENABLE); WWDG Clock Enable

2) Set the window value and divide number

The function that sets the window value is:

Voidwwdg_setwindowvalue (uint8_t windowvalue);

This function is a window value for an entry parameter, which is easy to understand. The function to set the number of dividers is:

Voidwwdg_setprescaler (uint32_t Wwdg_prescaler);

This function also has only one entry parameter, which is the crossover value.

3) Turn on WWDG interrupt and group

The function to turn on the WWDG interrupt is:

Wwdg_enableit ();//Open window watchdog interrupt

Next is the interrupt priority configuration, which is not repeated here, using the Nvic_init () function.

4) Set the counter initial value and enable the watchdog

This step is implemented in the library function through a function:

Voidwwdg_enable (uint8_t Counter);

The function sets both the counter initial value and enables the window watchdog to be enabled.

It is also necessary to illustrate that the library function also provides a separate function for setting counter values:

Voidwwdg_setcounter (uint8_t Counter);

5) Write Interrupt service function

In the end, it is also to write the window watchdog interrupt Service function, through this function to feed the dog, feed the dog fast, otherwise when the window watchdog counter value is reduced to 0x3f, it will cause a soft reset. The ewif bits of the status register are also emptied in the interrupt service function. three. Window watchdog source

Wwdog.h

#ifndef_WWDOG_H_H_H
#define_WWDOG_H_H_H
#include "stm32f4xx_wwdg.h"
voidwwdg_init (U8 tr,u8 WR, U32 fprer);
Voidwwdg_irqhandler (void);
#endif

Wwdog.c

#include "wwdog.h" #include "led.h"  //Save the setting value of the WWDG counter, the default is maximum.
u8wwdg_cnt=0x7f; Voidwwdg_init (U8 tr,u8 wr,u32 fprer) {  Nvic_inittypedef nvic_initstructure;  rcc_apb1periphclockcmd (RCC_ apb1periph_wwdg,enable); 
Enable window watchdog clock          wwdg_cnt=tr&wwdg_cnt;  //Initialize WWDG_CNT.   Wwdg_setprescaler (fprer); Set the crossover value   Wwdg_setwindowvalue (WR); Set window value//wwdg_setcounter (wwdg_cnt);//Set Count value   wwdg_enable (wwdg_cnt); //Turn on watchdog          NVIC_InitStructure.NVIC_IRQChannel=WWDG_IRQn; //window watchdog interrupt  nvic_initstructure.nvic_ irqchannelpreemptionpriority=0x02; //preemption priority is 2  NVIC_InitStructure.NVIC_IRQChannelSubPriority=0x03;                                   //Sub-priority is 3  NVIC_ Initstructure.nvic_irqchannelcmd=enable;&nBsp
Enable window watchdog   Nvic_init (&nvic_initstructure);          Wwdg_clearflag ()//clear wake-up interrupt flag bit   Wwdg_enableit ()//Start early wakeup interrupt}// Window watchdog interrupt Service program Voidwwdg_irqhandler (void) {  static int count = 0;   Wwdg_setcounter (WWDG_CNT);//Reset window watchdog value   Wwdg_clearflag ();//Clear early wake interrupt flag bit   if (count++% 2 = = 0)   {    led_operate (led_red,led_on); &nbsp ; }   Else   {    led_operate (Led_red,led_off);  }}

Main.c

#include "led.h" #include "key.h" #include "delay.h" #include "uart.h" #include "exit.h" #include "iwdog.h" Voiduser_delay
(__io uint32_t ncount)
{  while (ncount--)   { }} staticint count = 0; Intmain (void) {  #if 1  nvic_prioritygroupconfig (nvic_prioritygroup_2);//Set System Interrupt Priority Group 2   Delay_init ( 168); //Initialize delay function   Led_init ();                        //Initialize LED Port   Key_init ();                //initialization key   led_operate (led_blue,led_on);                  //Light LED0  
Delay_ms (300);   Wwdg_init (0x7f,0x5f,wwdg_prescaler_8);       //Counter value is 7f, window register is 5f, divide number is 8                 while (1)   {  &nbsP
Led_operate (Led_blue,led_off);  } #endif   }