"Turn" PCB Cabling Specification

Design process

A. Creating A network table

1. Network table is the schematic and PCB interface files, PCB designers should be based on the use of schematic and PCB design tool characteristics, choose the correct network table format, to create a network table that meets the requirements.

2. In the process of creating a network table, you should actively assist the schematic designer to troubleshoot errors according to the characteristics of the schematic design tool. Ensure the correctness and completeness of the network tables.

3. Determine the package (PCB footprint) of the device.

4. Create the PCB design document according to the board structure diagram or the corresponding standard plate frame;

Note that the location of the origin of the single-board coordinates is selected correctly, and the setting principle of the Origin point:

A. The junction of extension lines to the left and bottom of the veneer.

B. The first pad in the lower left corner of the veneer.

Round corners around the board frame, with a chamfer radius of 5mm. Special case reference structure design requirements.

B. Layout

1. Set the size of the board frame according to the structure diagram, and arrange the devices which need to be positioned by the structural elements such as mounting holes, connectors, etc., and give the devices non-movable properties. Dimensioning according to the requirements of the process design specification.

2. According to the structure diagram and the clamping edge required for production and processing, set the forbidden wiring area of the printed circuit board and prohibit the layout area. According to the special requirements of some components, the installation of the forbidden wiring area.

3. Take into account the PCB performance and processing efficiency selection process.

The preferred order of processing technology is: component surface single-sided placement-component surface-mount, plug-and-mix (component surface-mounted solder surface mount once wave-mounted)-double-sided mounting-component surface paste plug mixed, welded surface mount.

4. Basic principles of layout operations

A. In accordance with the "first big after small, first difficult after easy" layout principle, that is important unit circuit, core components should be prioritized layout.

B. The layout should refer to the schematic diagram, according to the main signal flow of the single board to arrange the main components.

C. The layout should meet the following requirements: The total wiring as short as possible, the shortest key signal line, high voltage, large current signal and small current, low voltage weak signal completely separate, analog signal and digital signal separation, high-frequency signal and low-frequency signal separation, high-frequency components of the interval to be sufficient.

D. The same structural circuit section, as far as possible the use of "symmetrical" standard layout;

E. Optimize the layout according to the standard of uniform distribution, center of gravity balance and beautiful layout;

F. Device layout grid settings, general IC device layout, the grid should be 50--100 mil, small surface mount devices, such as surface mount component layout, the grid should be set to not less than 25mil.

G. If there are special layout requirements, should be determined after the communication between the parties.

5. The same type of cartridge components should be placed in the X or Y direction in one Direction. The same type of polar discrete components also strive to be consistent in the X or Y direction for easy production and inspection.

6. Heating elements should be generally distributed evenly, in order to facilitate the cooling of the single board and the whole machine, in addition to temperature sensing components outside the temperature-sensitive devices should be away from the heat of large components.

7. The arrangement of components to facilitate commissioning and maintenance, that is, small components can not be placed around large components, the element to be debugged, the device around to have enough space.

8. A single board with a wave soldering process is required, and the mounting holes and locating holes of the fasteners shall be non-metallic holes. When the mounting hole needs grounding, the distribution ground hole should be used to connect with the ground plane.

9. Welding surface of the SMT components using the wave soldering process, the resistance, the capacity of the axial direction of the wave soldering with the orientation of the vertical, resistance and SOP (pin spacing greater than or equal to 1.27mm) components of the axial and transmission direction parallel; pin spacing is less than 1.27mm (50mil) of ICS, SOJ, PLCC, The active components such as QFP are prevented from soldering with wave soldering.

The distance between the BGA and the adjacent components is >5mm. The distance between the other SMD components >0.7mm; the outer side of the mounting element pad and the adjacent cartridge components is greater than 2mm, the PCB with crimp parts, the crimp of the connector around 5mm can not be inserted in the element, the device, in the welding surface around 5mm can not be affixed to the element, device.

The layout of IC decoupling capacitor should be as close as possible to the IC's power supply pin, and make it with the power supply and the shortest circuit formed between the ground.

12. When components are laid out, appropriate consideration should be given to using devices of the same power source as much as possible to allow for future power separation.

13. For impedance matching purposes, the layout of the blocking container should be arranged according to its properties.

The layout of the series matching resistor is close to the driving end of the signal, and the distance generally does not exceed 500mil.

Matching resistor, capacitance layout must distinguish between the source end of the signal and the terminal, for multi-load terminal matching must be at the far end of the signal to match.

14. After the layout is finished, print out the assembly diagram for the schematic designer to check the correctness of the device package, and confirm the signal correspondence between the veneer, backplane and connector, and then start wiring after confirming the error.

C. Setting routing Constraints

1. Report Design Parameters

After the layout is basically determined, apply the statistical function of the PCB design tool, report the network number, network density, average pin density and other basic parameters, in order to determine the required number of signal wiring layer.

The number of signal layers can be determined by reference to the following empirical data

Pin density signal Layer Number board layer

1.0 + 2 2

0.6-1.0 2 4

0.4-0.6 4 6

0.3-0.4 6 8

0.2-0.3 8 12

<0.2 >14

Note: Pin density is defined as: Board area (square inch)/(total number of pins on board/14)

The specific determination of the number of cabling should also consider the reliability requirements of the single Board, the speed of operation of the signal, manufacturing costs and lead time and other factors.

1. Wiring layer setup in the high-speed digital circuit design, the power supply and the stratum should be together as far as possible, the middle does not arrange the wiring. All the wiring layers are as close as possible to a plane layer, preferably in the plane as a route isolation layer.

In order to reduce the electromagnetic interference of inter-layer signal, the direction of signal line of adjacent wiring layer should be perpendicular.

The 1--2 impedance control layer can be designed according to the need, if more impedance control layer needs to consult with the PCB home. The impedance control layer should be clearly marked as required. The network cabling with the impedance control requirements on the veneer is distributed on the impedance control layer.

2. Set line width and line spacing and line spacing settings to consider factors

A. Density of veneer. The higher the density of the plates, the greater the tendency to use finer lines and narrower clearances.

B. The current intensity of the signal. When the average current of the signal is large, the current that can be carried by the cabling width should be considered, and the line width can refer to the following data:

PCB design of copper foil thickness, trace width and current relationship

The flow rate of copper foil with different thickness and width is shown in the following table:

Copper skin thickness 35um copper skin thickness 50um copper skin thickness 70um

Copper skin Δt=10℃ Copper skin Δt=10℃ Copper Skin Δt=10℃

Note:

I. When using copper skin as wire through a large current, the copper foil width of the load flow should refer to the table of the value of the derating 50% to choose to consider.

Ii. in PCB design and processing, commonly used Oz (oz) as the thickness of the copper Unit, 1 oz copper thickness is defined as 1 square feet area of copper foil weight of one Anglo, corresponding to the physical thickness of 35um;2oz copper thickness of 70um.

C. Circuit operating voltage: The setting of the line spacing should consider its dielectric strength.

D. Reliability requirements. When reliability requirements are high, they tend to use wider cabling and greater spacing.

E. PCB Processing Technology Limitations

Domestic and international advanced level

Recommended minimum line width/pitch 6mil/6mil 4mil/4mil

Limit min. line width/pitch 4mil/6mil 2mil/2mil

1. Hole setting over-line hole

The minimum pore size of the plate is determined by the thickness of the plate, and the thickness aperture ratio should be less than 5--8.

The Aperture optimization series is as follows:

Aperture: 24mil 20mil 16mil 12mil 8mil

Pad Diameter: 40mil 35mil 28mil 25mil 20mil

Inner Thermal pad Size: 50mil 45mil 40mil 35mil 30mil

The relationship between plate thickness and minimum aperture:

Board Thickness: 3.0mm 2.5mm 2.0mm 1.6mm 1.0mm

Min. aperture: 24mil 20mil 16mil 12mil 8mil

Blind holes and buried holes

The blind hole is a through hole connecting the surface and the inner layer without penetrating the whole plate, and the buried hole is connected between the inner layer and

The vias are not visible on the surface of the plate, and these two types of vias can refer to the vias.

The use of blind hole and buried hole design should be fully aware of the PCB processing process, to avoid the PCB processing belt

Need to consult with the PCB supplier if necessary.

Test hole

Test holes are used for ICT testing purposes of the vias, can also be done through the hole, in principle, no limit to the diameter of the pad should not be less than 25mil, the center distance between the test hole is not less than 50mil.

Component weld holes are not recommended as test holes.

2. Special wiring interval Setting special wiring interval refers to some special areas on the veneer need to use different from the general settings of the wiring parameters, such as some high-density devices need to use the finer line width, smaller spacing and smaller vias, or some network wiring parameters adjustment, need to be confirmed and set up before wiring.

3. Define and split the plane layer A. The plane layer is generally used for the power supply and formation of the Circuit (reference layer), because the circuit may be used in different power and strata, the power layer and strata need to be separated, the separation width to consider the difference between different power supply, the potential difference is greater than 12V, the separation width of 50mil, conversely Optional 20--25mil.

B. Plane separation consider the integrity of the high-speed signal reflow path.

C. When the return path of the high-speed signal is compromised, the additional wiring layer should be compensated. For example, a grounded copper foil is used to enclose the signal network to provide a ground circuit of the signal.

B. Pre-routing simulation (layout evaluation, pending expansion)

C. Cabling

1. Cabling priority key signal line priority: power supply, touch small signal, high-speed signal, clock signal and synchronization signal, such as key signal priority wiring

Density priority principle: the wiring is initiated from the most complex devices connected on a single board. Start cabling from the most densely populated area on a single board.

2. Automatic cabling in the case of the quality of the cabling to meet the design requirements, you can use automatic router to improve the efficiency of the automatic wiring before the following preparations should be completed:

Automatic routing control file (do file)

In order to better control the quality of cabling, generally before running to define the wiring rules, these rules can be defined in the software's graphical interface, but the software provides a better control method, that is, for the design situation, write out the automatic routing control file (do file), the software under the control of the file run.

3. As far as possible for the clock signal, high-frequency signal, sensitive signal and other key signals to provide a dedicated wiring layer, and ensure its minimum loop area. If necessary, manual priority wiring, shielding and increased safety spacing should be adopted. Guaranteed signal quality. 4. The EMC environment between the power supply layer and the formation is poor, avoid the layout of interference sensitive signals. 5. Networks with impedance control requirements should be placed on the impedance control layer. 6. Rules that should be followed in PCB design 1) ground loop rules: loop minimum rule, that is, the signal line and the loop area of the circuit to be as small as possible, the smaller the ring area, the less radiation to the external, the reception of external interference is smaller. In view of this rule, in the ground plane division, we should take into account the distribution of the ground plane and the important signal route, and prevent the problem caused by the ground plane slotting, etc. in the double board design, in the case of leaving enough space for the power supply, the left part should be filled with reference, and the necessary holes will be added to the signal For some key signals as far as possible to use ground insulation, some high frequency design, the need to consider its ground plane signal circuit problem, it is advisable to use multilayer board.

2) harassed control

Crosstalk (CrossTalk) refers to the different networks on the PCB due to the long parallel wiring caused by mutual interference, mainly due to the distribution of parallel lines between the capacitance and the role of distributed inductance. The main measures for overcoming crosstalk are:

Increase the spacing of parallel cabling and follow the 3W rules.

Insert a grounded isolation line between parallel lines.

Reduce the distance between the routing layer and the ground plane.

3) Shielding Protection

The corresponding ground circuit rules, in fact, in order to minimize the signal loop area, more common in some of the more important signals, such as clock signal, synchronous signal, for some particularly important, frequency is particularly high signal, should consider the use of copper shaft cable shielding structure design, will be the line of the wire off and around with ground insulation, Moreover, we should consider how to effectively combine the shielding and the actual plane.

4) Direction control rules of the route:

That is, the direction of the adjacent layer is orthogonal structure. Avoid the different signal lines in the adjacent layer in the same direction, to reduce unnecessary interlayer harassed, when due to plate structure constraints (such as some backplane) difficult to avoid the situation, especially the high signal rate, should consider the ground plane to isolate the wiring layer, the ground signal line to isolate the signal lines.

5) Open-loop inspection rules for the route:

It is generally not permissible to have one end of a floating cable (dangling line),

Mainly to avoid the "antenna effect", reduce unnecessary interference radiation and acceptance, otherwise it may bring unpredictable results.

6) Impedance matching check rule:

The wiring width of the same network should be consistent, the change of line width will cause the line characteristic impedance is uneven, when the transmission speed is high, will produce reflection, in the design should try to avoid this situation. In some conditions, such as connector lead wire, BGA package of similar structure, may not avoid the line width changes, should minimize the effective length of the intermediate inconsistencies.

7) Route End network rules:

In high-speed digital circuit, when the delay time of PCB cabling is greater than 1/4 of the signal rise time (or fall time), the wiring can be regarded as transmission line, in order to ensure that the input and output impedance of the signal and the impedance of the transmission line correctly match, you can use a variety of forms of matching methods, The matching method is related to the connection mode of the network and the topological structure of the cabling.

A. For a point-to-point (one output for one input) connection, you can choose the beginning of series matching or terminal parallel matching. The former is simple in structure and low in cost, but has higher delay. The latter matching effect is good, but the structure is complex and the cost is higher.

B. For point-to-multipoint (one output corresponds to multiple outputs) connection, when the topology of the network is daisy chain, should choose the terminal parallel matching. When the network is a star structure, you can refer to the point-to-point structure.

Star and Daisy chains are two basic topologies, other structures can be seen as deformation of the basic structure, and some flexible measures can be taken to match. In the actual operation to take into account the cost, power and performance factors, generally do not pursue an exact match, as long as the mismatch caused by the reflection and other interference limits in an acceptable range.

8) loop Check rule:

Prevents the signal line from forming a self-loop between different layers. This kind of problem is apt to occur in multilayer board design, and the self-ring will cause radiation interference.

9) The branching length control rules for the route:

As far as possible to control the length of the branch, the general requirement is TDELAY<=TRISE/20.

10) The resonant rules of the route:

Mainly for high-frequency signal design, that is, the length of the wiring should not be an integer multiples of its wavelength, so as not to produce resonance phenomenon.

11) Route length control rules:

Short-term rules, in the design should try to make the length of the wiring as short as possible, in order to reduce the excessive length of the interference caused by the problem, especially some important signal lines, such as clock line, be sure to put its oscillator near the device. In case of driving multiple devices, the network topology should be determined according to the specific circumstances.

12) Chamfer rule:

Avoid sharp angles and right angles in PCB design,

Produce unnecessary radiation, while the process performance is not good.

13) device Decoupling rule:

A. Add the necessary decoupling capacitors to the printed version, filter out the interference signal on the power supply, and stabilize the power supply signal. In the multilayer board, the position of the decoupling capacitor is generally not very high, but on the double-layer board, the layout of the decoupling capacitor and the wiring mode of the power supply will directly affect the stability of the whole system, and sometimes even related to the success or failure of the design.

B. In the double board design, the general should make the current through the filter capacitor filter and then for the device to use, but also fully consider the device generated by the power supply noise on the downstream devices, in general, the use of bus structure design is better, at design time, Also consider the impact of the voltage drop caused by the long transmission distance to the device, add some power filter loop, if necessary, to avoid potential difference.

C. In the high-speed circuit design, whether the decoupling capacitor can be used correctly affects the stability of the whole board.

14) Device Layout partitioning/layering rules:

A. The main purpose is to prevent interference between modules of different operating frequencies, while minimizing the length of the high-frequency portion of the wiring. Usually the high-frequency part is laid in the interface section to reduce the length of the wiring, of course, such a layout will still take into account the low-frequency signal may be disturbed. At the same time, we should take into account the high/low frequency partial ground plane segmentation problem, usually use the ground division of the two, and then at the interface single point-to-phase.

B. For hybrid circuits, there are also analog and digital circuits arranged on both sides of the printed board, respectively, using different layers of wiring, the middle of the formation of isolation.

15) isolated Copper Zone control rules:

The emergence of isolated copper zones will bring some unpredictable problems, so isolating copper areas with other signals can help improve signal quality,

The isolated copper zone is usually grounded or removed. In the actual production, PCB manufacturers will be some of the vacant parts of the board to increase some copper foil, which is mainly for the convenience of printing board processing, at the same time to prevent the printing board warping also has a certain role.

16) Integrity rules for power and ground layers:

For the area with dense conduction hole, it is important to avoid the connection between the hole in the hollowing area of the power supply and the formation, and to form the division of the plane layer, thus destroying the integrity of the plane layer and causing the loop area of the signal line to increase in the stratum.

17) Overlapping power and ground layer rules:

The different power layers have to avoid overlapping in space. Mainly in order to reduce the interference between different power supply, especially some voltage difference between the power supply, the power plane overlap problem must try to avoid, it is difficult to avoid when you can consider the middle interval strata.

3W Rules:

In order to reduce inter-line crosstalk, should ensure that the line spacing is large enough, when the line center spacing is not less than 3 times times the line width, you can maintain 70% of the electric field does not interfere with each other, called the 3W rule. To achieve 98% of the electric field does not interfere with each other, you can use the spacing of 10W.

20H Rules:

Because the electric field between the power layer and the stratum is changed, the electromagnetic interference is radiated outward at the edge of the plate. Called Edge effect.

The solution is to shrink the power supply layer so that the electric field is conducted only within the range of the ground plane. In the case of an H (the medium thickness between the power supply and the ground), if the inner 20H can limit 70% of the electric field to the edge of the ground plane, the internal contraction of 100H can limit 98% of the electric field.

20) Five---five rules:

PCB layer selection rules, that is, clock frequency to 5MHz or pulse rise time is less than 5ns, the PCB board shall be multi-layer board, which is the general rule, sometimes for cost and other factors, the use of double-board structure, in this case, it is best to the printed board side as a complete ground plane layer.

D. Post-simulation and design optimization (to be supplemented)

E. Process Design Requirements

1. General process design requirements refer to the "Printed circuit CAD Process Design Code" q/dkba-y001-1999 2. ICT testability requirements for functional boards

A. For high-volume production of veneer, generally in the production of ICT (in the circuit test), in order to meet the requirements of ICT testing equipment, PCB design should do the corresponding treatment, the general requirements of each network must have at least one Test probe to contact the testing point, known as the ICT test point.

B. The number of ICT test points on the PCB should conform to the requirements of the ICT test specification, and should be in the welding surface of the PCB board, the detection point can be the solder point of the device, can also be a hole.

C. The minimum pad size of the test point is 24mils (0.6mm) and the minimum spacing of two individual test points is 60mils (1.5mm).

D. A single board that requires ICT testing to design two 125MILS non-metallic holes on the diagonal of the PCB for positioning ICT testing.

3. PCB Labeling specifications. The precise dimensions of the printed board should be indicated in the drilling layer, and no closed dimensions can be formed, and the dimensions and quantities of all holes are indicated and the holes are metallized.

II. Design Review

A. After the review process design is completed, according to the needs of the PCB designer or product hardware developers to put forward the PCB design quality review, its work flow and review methods see the PCB Design Review specification.

B. Self-test project

If you do not need to organize a review team for design review, you can check the following items yourself.

1. Check the high-frequency, high-speed, clock and other vulnerable signal lines, whether the loop area is the smallest, is away from the source of interference, whether there are redundant vias and winding, whether there is a collapse of the Stratigraphic division area

2. Check the crystal, transformer, optical lotus, power module below whether there is a signal line through, should try to avoid stringing under it, especially the crystal should be laid as far as possible grounding the copper skin.

3. Check whether the locating hole, the positioning piece is consistent with the structure diagram, ICT positioning hole, SMT positioning cursor is added and meet the process requirements.

4. Check whether the serial number of the device is in accordance with the principle of left-to-right, and there is no screen cover pad; Check that the version number of the silk screen conforms to the version upgrade specification and identifies it.

5. Report whether the completion of the cabling is 100%, whether there are thread threads, and whether there are isolated copper skins.

6. Check the power supply, the ground is divided correctly, the single point has been processed;

7. Check each layer light drawing option is correct, the label and the light drawing name is correct;

8. Output the light drawing file, check with CAM350, confirm that the light drawing is generated correctly.

9. Complete the PCB Design (archive) Self-test form as required and submit it together with the design document to the process designer for process review.

10. The problems identified in the process review are actively improved to ensure the machinability, workability and testability of the veneer.

"Turn"  PCB Cabling Specification