"Turn" STM32 independent watchdog introduction

The independent watchdog of the STM32 is driven by an internal dedicated 40Khz low-speed clock, which is still valid even if the master clock fails .

The principle of watchdog: SCM System in the external interference will appear in the program to run the phenomenon of flying caused by the death cycle, watchdog circuit is to avoid the occurrence of this situation. The function of the watchdog is to realize the automatic reset of the processor (sending the reset signal) by not receiving the dog feed signal (which means that the MCU is already dead) within a certain time (through the timer counter).

write 0xCCCC in the key-value register (iwdg_kr )to start enabling the standalone watchdog, at which point the counter starts to decrement from its reset value of 0xFFF count. When the counter is counted to the end of 0x000, a reset signal (Iwdg_reset) is generated. Whenever the key register Iwdg_kr is written to 0xAAAA, the value in the IWDG_RLR is reloaded into the counter to avoid a watchdog reset.

The IWDG_PR and IWDG_RLR registers have write-protected functions. To modify the values of these two registers, you must first write the 0x5555 to the IWDG_KR register. Writing other values to this register will disrupt the sequence of operations and the registers will be re-protected. A reload operation (that is, write 0xAAAA) also initiates the Write protection feature.

As long as the above three registers are set accordingly, we can start the STM32 independent watchdog, the boot process can be implemented as follows (independent watchdog-related library functions and definitions are distributed in Files Stm32f10x_iwdg.h and stm32f10x_iwdg.c):

1) Cancel Register write protection (write 0x5555 to IWDG_KR)

With this step, we cancel the write protection of IWDG_PR and IWDG_RLR so that the two registers can be manipulated later, setting the values of IWDG_PR and IWDG_RLR. This implementation function in the library function is:

Iwdg_writeaccesscmd(iwdg_writeaccess_enable);

2) set the Prescaler factor and reload value of the independent watchdog

The function to set the frequency division factor for the watchdog is:

void Iwdg_setprescaler(uint8_t iwdg_prescaler); Setting the IWDG prescaler value

The function to set the watchdog's reload value is:

void iwdg_setreload(uint16_t Reload);//Set IWDG reload value

Set the frequency divider factor Prer and reload value of the watchdog to know the watchdog time (that is, the watchdog overflow time), the time is calculated as follows:

Tout= ((4x2^prer) XRLR)/40

Where Tout is the watchdog overflow time (in MS), Prer is the watchdog clock Prescaler value (iwdg_pr value), and the range is 0~7;RLR as the watchdog's reload value (IWDG_RLR value);

For example, we set the Prer value to 4, RLR value is 625, then you can get tout=64x625/40=1000ms, so that the watchdog overflow time is 1s, as long as you in a second, once written 0XAAAA to IWDG_KR, will not cause the watchdog reset (when It is also possible to write multiple times). Here to remind you that the watchdog clock is not accurate 40Khz, so when feeding the dog, it is best not too late, otherwise, there may be a watchdog reset.

3) Reload count value feed dog (write 0XAAAA to IWDG_KR)

Functions that overload the count value inside a library function are:

Iwdg_reloadcounter (); Reload the IWDG counter according to the value of the IWDG reload register

By this sentence, the STM32 will reload the IWDG_RLR value into the watchdog counter. That is to achieve the independent watchdog dog feeding operation.

4) start watchdog (write 0XCCCC to IWDG_KR)

The function that launches the independent watchdog inside the library function is:

Iwdg_enable (); Enable to IWDG

Through this sentence, to start the STM32 watchdog. Note that once enabled, the IWDG can no longer be turned off! Want to shut down, can only restart, and after restarting can not open IWDG, otherwise the problem is still, so here to remind you, if not IWDG, do not open it, lest trouble.

Click ( here) to collapse or open

2. #include "Sys.h"
4. #include "Iwdg.h"
8. /**
10. * Initialization of Independent watchdog
12. * Prer: Divide number: 0~7 (only low 3 bit valid!)
14. * Divide factor =4*2^prer. But the maximum value is only 256!
16. * RLR: Reload Register Value: Low 11 bits valid.
18. * Time Calculation (approximate): tout= ((4*2^prer) *RLR)/40 (ms).
20. */
22. void Iwdg_init(U8 prer, U16 rlr)
24. {
26. Iwdg_writeaccesscmd(iwdg_writeaccess_enable); /* Enable write operations on registers IWDG_PR and IWDG_RLR */
28. Iwdg_setprescaler(prer); /* Set IWDG Prescaler value: Set IWDG prescaler */
30. Iwdg_setreload(rlr); / * Set IWDG reload value * /
32. Iwdg_reloadcounter(); / * Reload the IWDG counter as per the value of the IWDG reload Register * /
34. Iwdg_enable(); / * Enable iwdg*/
36. }
40. /**
42. * Feed independent watchdog
44. */
46. void Iwdg_feed(void)
48. {
50. Iwdg_reloadcounter(); /*reload*/
52. }

"Turn" STM32 independent watchdog introduction