Read/write NAND flash analysis on S3C2410

Author: Liu Hongtao, Senior Lecturer at Huaqing vision embedded College.

I. Structure Analysis

The S3C2410 processor integrates an 8-bit nandflash controller. Currently, the eight most common nandflash players on the market include Samsung k9f1208, k9f1g08, and k9f2g08. The data page sizes of k9f1208, k9f1g08, and k9f2g08 are 512 bytes, 2 Kbyte, and 2 Kbyte, respectively. They differ in addressing methods, so program code is not universal. This article uses the S3C2410 processor and the k9f1208 system as an example to describe the nandflash read/write method.

Nandflash data is stored in the memory cell in bit mode. Generally, only one bit can be stored in a cell. These cells are connected to a bit line in 8 or 16 units, form the so-called byte (X8)/Word (x16), which is the location width of the NAND device. These lines form pages, and the pages form a block. The related data of k9f1208 is as follows:

1 block = 32 page; 1 page = 528 byte = 512 byte (main area) + 16 byte (spare area ).

Total capacity = 4096 (Block quantity) * 32 (page/block) * 512 (byte/Page) = 64 Mbyte

Nandflash reads and writes data on pages, while data is erased on blocks. According to the k9f1208 organization mode, there are four types of addresses: column address, halfpage pointer, page address, and block address. A [0: 25] indicates the address of the data in 64 MB space.

Column Address indicates the data address on the half page. The size range is 0 ~ 255, represented by;

Halfpage pointer indicates the position of the half page on the whole page, that is, the position between 0 and ~ 255 space is still in 256 ~ 511 space, represented by a [8;

Page Address indicates the address of the page in the block. The size range is 0 ~ 31, represented by;

Block Address indicates the position of the block in flash. The size range is 0 ~ 4095, represented by;

Ii. Read operation process

The addressing of k9f1208 is divided into four cycle nodes. They are: A [], a [], a [], and a [25].

The read operation process is as follows: 1. Sending read instructions; 2. Sending 1st Cycle addresses; 3. Sending 2nd Cycle addresses; 4. Sending 3rd cycle addresses; 5. Send 4th cycle addresses; 6. Read data to the end of the page.

K9f1208 provides two read commands: '0x00' and '0x01 '. The difference between the two commands is that '0x00' can set a [8] to 0 and select the last half of the page; while '0x01' can set a [8] to 1 and select the next half of the page.

Although the read/write process does not start from the page boundary, we recommend that you read and write from the page boundary until the page ends. The following describes the read process by analyzing the code for reading the page.
Static void readpage (u32 ADDR, u8 * BUF) // ADDR indicates the page number in flash, that is, 'Flash address> 9'
{
2010i;
Nfchipen (); // enable nandflash
Wrnfcmd (read00000); // sends the READ command '0x00'. The command '0x00' is used for reading the entire page'
Wrnfaddr (0); // the first cycle of the write address, that is, column address. Since the whole page is read, 0 is obtained.
Wrnfaddr (ADDR); // 2nd cycle of the write address, that is, a []
Wrnfaddr (ADDR> 8); // 3rd cycle of the write address, that is, a []
Wrnfaddr (ADDR> 16); // 4th cycle of the write address, that is, a [25].
Waitnfbusy (); // wait for the system to be busy
For (I = 0; I <512; I ++)
Buf [I] = rdnfdat (); // read 1 page of Data cyclically
Nfchipds (); // release nandflash
}

Iii. write operation process

The write operation process is: 1. Sending the Write Start command; 2. Sending 1st Cycle addresses; 3. Sending 2nd Cycle addresses; 4. Sending 3rd cycle addresses; 5. Send 4th cycle addresses; 6. Write Data to the end of the page; 7. Send the write end command.

The following describes the read/write process by analyzing the code written to the page.
Static void writepage (u32 ADDR, u8 * BUF) // ADDR indicates the page number in flash, that is, 'Flash address> 9'
{
U32 I;
Nfchipen (); // enable nandflash
Wrnfcmd (prog00000); // sends the Write Start command '0x80'
Wrnfaddr (0); // 1st cycle of the write address
Wrnfaddr (ADDR); // 2nd cycle of the write address
Wrnfaddr (ADDR> 8); // write 3rd cycle addresses
Wrnfaddr (ADDR> 16); write 4th cycle addresses
Waitnfbusy (); // wait for the system to be busy
For (I = 0; I <512; I ++)
Wrnfdat (BUF [I]); // write 1 page of Data cyclically
Wrnfcmd (progcmd1); // sends the write end command '0x10'
Nfchipds (); // release nandflash
}

Iv. Summary

Taking the S3C2410 processor and the k9f1208 system as examples, this article describes the read/write process of NAND Flash. Bad blocks are not taken into account during reading and writing. The ECC and bad block processing problems will be discussed in the next topic.