Real mode/protection mode, meaning of Gdt/ldt

1, real mode, protection mode
There are two modes of CPU Startup: Real mode and protection mode

Real mode: cannot use multithreading. You cannot implement a permission rating. You cannot access more than 20-bit address lines, which means you can access only 1 m memory (!!!)
Address Translation formula is: Physical address = Linear address = Segment Address *16 + segment offset

Protection mode: the operating system (the HEAD.S program in the system module) takes over the CPU and causes the CPU to enter protection mode.
Includes CPU permission ratings. Multi-task, memory paging and other functions.

2. Address Translation Steps

Address Translation: Recall gdt--> search Ldt--> Find segment (determine segment base)--> determine linear address = Segment Base + offset--> Physical address = Linear Address + paging

The segment register is no longer the base address of the addressable segment, but rather the index value of a descriptor entry in the table for a Segment descriptor table.

Global Segment Descriptor Table: An array on a linear address space. Each structure cell represents the meaning of a "segment": Janki address (BASE) and size (LIMIT) that participate in the conversion process of the logical address.

Local Segment Descriptor Table: Each task usually uses a LDT sheet. As an extension of the GDT table.
(in Linux, the 4 main segment descriptors-
User state code Segment/user state data Segment/kernel state code segment/kernel state data segment
are set to base=0x0000000, LIMIT=0XFFFFFFFF)

3, Gdt,ldt

(1) Global descriptor Table GDT Global descriptor Tables GDT only one (one processor corresponds to one GDT), GDT can be placed anywhere in memory, but the CPU must know the GDT entrance, Where the base address is located, the Intel Designer door provides a register GDTR used to hold the GDT entry address, the programmer will GDT set in the memory of a location, you can through the LGDT instructions to the GDT of the entry address into this register, and thereafter, The CPU accesses the GDT based on the contents of this register as a GDT entry. The GDTR store is the base address of the GDT in memory and its table length boundaries.

(2) the segment selector (Selector) is accessed by the GDTR Global Descriptor (GDT) by the "segment selector" (the segment register in real mode (my personal understanding of the CS register), as shown in Figure three ① steps. The segment selector is a 16-bit register (same as the segment registers in real mode) as shown in Figure four

The segment selector includes three parts: Descriptor index, TI, request privilege level (RPL). His index (descriptor) section denotes the position of the required segment in the description chart (my understanding is to find the corresponding segment in the GDT or LDT according to the index in the CS register), The corresponding descriptor (such as figure three ① step) can be found by this position and then based on the descriptor base address stored in the GDTR. Then, using the segment base in the Descriptor table plus the OFFSET of the logical address (sel:offset), you can convert to a linear address (as in Figure three ② steps), the TI value in the segment selector is only one 0 or 1, 0 represents the selector in the GDT selection, and 1 represents the selector in the LDT selection. The request privilege level (RPL) represents the privilege level of the Select Child, with a total of 4 privilege levels (level 0, 1, 2, 3).

A description of the privilege level: each segment of a task has a specific level. Whenever a program tries to access a segment, it compares the privilege level owned by the program to the privilege level to be accessed to determine whether the segment can be accessed. System Convention, the CPU can only access segments of the same privilege level or lower privileged level.

For example, give a logical address: 21h:12345678h to linear address a. Select the son sel=21h=0000000000100 0 01b He means: The index=4 of the selector is the 4th descriptor in the 100b selection GDT; ti= 0 The selector is selected in the GDT, and the left 01b represents the privileged level rpl=1 B offset=12345678h If at this time GDT the segment base (base) described in the fourth descriptor is 11111111h, then the linear address =11111111h+12345678h= 23456789h

3 The Local Descriptor Table LDT (the local Descriptor table) can have several sheets, each task can have one. We can understand GDT and LDT:GDT as a first-level descriptor table, LDT a two-level descriptor list. As shown in figure

Ldt and GDT are essentially the same, but Ldt nested in GDT. LDTR records the starting position of the local descriptor chart, and the contents of the GDTR different ldtr are a segment selector. Since the LDT itself is also a section of memory, it also has a descriptor that describes it, which is stored in the GDT, and there is a selector for that descriptor, which LDTR load is such a selector. LDTR can be changed at any time in the program by using the Lldt instruction. As shown above, if the load is selector 2 then LDTR is pointing to table LDT2.

For example, if we want to select the address 12345678h of the segment described by the third Descriptor in table LDT2.

1. First you need to mount LDTR so that it points to LDT2 using instructions Lldt load Select2 to LDTR

2. The INDEX=3 representative of the SEL selects the third descriptor when it is accessed through a logical address (sel:offset); the ti=1 represents the selector in LDT selection, at which point ldtr points to LDT2, so it is selected in LDT2, at which point the SEL value is 1Ch (binary is 11 1 00b). offset=12345678h. Logical address is 1c:12345678h

3. Select the descriptor from the SEL, with the base address (base) in the descriptor, plus offset, to get the linear addresses, such as the base address is 11111111h, then the =11111111h+12345678h=23456789h

4. At this point, if you want to access the third descriptor in LDT1, just use the Lldt instruction to mount the selector selector 1 and then perform 2 or 32 steps (because LDTR points to LDT1 at this point) because each process has its own set of program segments, data segments, stack segments, With a local descriptor chart, you can encapsulate the program segments, data segments, and stack segments of each process, so that you can access segments of different processes as long as you change the LDTR.

http://blog.csdn.net/lianxi1999/article/details/1799298

1.

Because the CPU uses the logical addr.   In order for the CPU to work properly, we need to provide it with a variety of registers to logical addr.         2. Maintain multiple process switching information. The A.GDTR register points to the GDT's first address in memory.        Use the content in Cs,ds as segment selector.           B.CS the top 13 digits as index, the lowest 2 bits used to determine whether the CPU is running at 0 or 3 (DPL), and the remaining one indicates access GDT or LDT.        Gdt/ldt table entries have DPL, the CPU to access it when compared to the minimum two bits and GDT table entries in the DPL, passed the check to continue access. The C.TSS (status segment) is a special segment. The CPU registers are pressed into the stack before the process switches

The segment registers in protected mode are composed of 16-bit selectors and 64-bit segment descriptor registers.

Segment Descriptor Register: Storage Segment Descriptor selector: Index of the storage segment descriptor

PS: The original real mode of the various segments of the register as a protection mode of the segment selector, 80486 has 6 (that is, cs,ss,ds,es,fs,gs) 80-bit segment registers, while providing 6 segments of the machine currently running the address space. The segment represented by the selector CS is still a code snippet, and the segment that the selector SS corresponds to is still a stack segment

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Segment Descriptor :

The

p,present bit, 1 indicates that the described segment exists (valid), and 0 indicates that the described segment is invalid, which causes an exception dpl,descriptor privilege, a descriptor privilege level, which describes the privilege level of the described segment DT, The descriptor type bit, 1 indicates that the current descriptor is a storage segment descriptor, and 0 is a system descriptor or a door descriptor. The TYPE: bit 0:a (accessed) bit indicating whether the descriptor has been accessed, and when the selection child is loaded into the segment register, the bit is marked as 1 bit 3:e (executable?) A bit, 0 describes the segment as a data segment, 1 is an executable segment (code snippet) When the data segment is, the bit 1 is a w bit to indicate whether the data segment is writable (0 read-only, 1 writable) bit 2 is Ed bit, indicating the extension direction of the segment (0 to High, 1 to low) when the executable segment is, bit 1 is r bit, indicating whether the execution segment is readable (0 is only executed, 1 readable) bit 2 is a C-bit, 0 indicates that the segment is not a consistent code segment (normal code snippet), 1 is a consistent code segment g is a granularity bit, and 0 indicates that the granularity of limit is byte. 1 is 4K bytes. D-bit: 1. In the executable segment, D is 1, which means that 32-bit addresses, 32/8-bit operands, 0-bit addresses are used, 16/ 8-bit operand 2. The Segment descriptor (stack segment?) that is addressed by the SS. , D is 1 for implied operations (such as Push/pop) using ESP as the stack pointer,/ for 0 using an SP (implied operation: Undefined segment property type use16/use32?66h,67h?) 3. In the lower-extended storage segment, D is 1, the upper bound for the segment is 4G; 0 is 64K The structure of the storage segment descriptor represents:

Subsection management can convert a virtual address to a linear address, and paging management can further translate a linear address into a physical address. When the PG position in the CR0 is 1 o'clock, the paging management function is started, for 0 o'clock, this prevents the paging management function from starting and uses the linear address as the physical address.

Virtual address converted to linear address:

Linear address = Janki Point + offset address

32-bit linear address to physical address: 32-bit is divided into: Page Directory index: Up to 10 digits, indicating the page table of Contents Table Descriptor Page Table index: 12 to 21 digits, and 10 bits. Indicates the number of page descriptor page descriptors in this page table: the low 12 bit of the linear address is the offset within the page.