Registers for ARM processors

In the arm system, there are usually the following 3 ways to control program execution:

* * During normal execution, each arm instruction is executed, the value of the program counter (PC) is incremented by 4 bytes , and the program Counter Register (PC) is incremented by 2 bytes for each thumb instruction executed. The entire process is executed sequentially.

* * Jump instruction, the program can jump to a specific address label execution, or jump to a specific subroutine to execute. Where theb instruction is used to perform a jump operation , and the BL instruction performs a jump operation while saving the subroutine

The return address of the sequence ; bx instruction in the execution of the jump operation, according to the target address for the program can be switched to the thumb State; The BLX instruction performs 3 operations, jumps to the destination address to execute, saves the subroutine's return

Address, depending on the destination address, you can switch the program to the thumb state.

* * When an abnormal interrupt occurs, when the system finishes executing the current instruction, it jumps to the appropriate exception interrupt handler to execute. When the exception interrupt handler finishes executing, the program returns to the next point where the interrupt instruction occurred

The order is executed . When the exception interrupt handler is entered, the execution site of the interrupted program is saved, and the execution scene of the interrupted program is resumed when exiting from the exception interrupt handler.

There are 37 registers for ARM processors. These include:
**31 a universal register, including a program counter (PC). These registers are all 32-bit registers.

**6 a status register. These registers are all 32-bit registers.

There are 7 different processor modes in the ARM processor, with a set of corresponding register groups in each mode. At any time, the visible registers include 15 universal registers (R0-R14), one or two status registers, and a program counter (PC). In all registers, some are public one physical register for each mode, and some registers have their own independent physical registers.

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General purpose Registers

8

The general register is divided into three categories: backup register, non-backup register, program counter PC

No backup registers

No backup registers include R0-R7. for each non-backup register, the same physical register is used for all processor modes . Non-backup registers are not used by the system for special purposes, and no backup registers can be used where universal registers are available.

Backup Registers

For a r8-r12 backup register, each register corresponds to two different physical registers. The system uses the backup register for any special purpose, but when the interrupt processing is very simple, when using only the R8-r14 register, the Fiq handler can make the interrupt processing very fast by eliminating the need to perform the save and restore instructions for the interrupted scene.

For R13,r14 backup registers, each register corresponds to six different physical registers, one of which is shared between the system mode and the user mode, and the other five corresponds to the other five processor modes. Use the following notation to differentiate each physical register:

R13_<mode>

Where mode can be one of several modes:Usr,svc,abt,und,irq,fiq

R13 is often used as a stack pointer; R14 (LR) is often used as the return address of a subroutine

The role of LR (R14), this LR generally has two functions:
1. When using BL or BLX to jump to a sub-process, R14 saves the return address and can be resumed at the end of the call process.
2. When an abnormal interrupt occurs, this exception mode-specific physical R14 is set to the address that the exception mode will return.

In addition, note that the PC, when debugging display is the current instruction address, and with MOV lr,pc when LR is saved is this instruction to the number of two instructions to the address , we can try to use MOV pc,pc, the result is jump two instructions, This is due to the fact that ARM's pipeline resulted in the prefetching of two instructions .

Program Counter PC

Can be used as a general general purpose register, but some directives have some limitations when using R15. Because ARM uses the pipelined processor mechanism, when the value of the PC is read correctly, the value is added to the current instruction address value by 8 bytes. That is, for the arm instruction set, the PC points to the address of the next two instructions of the current instruction . Since arm instructions are word-aligned, the No. 0 and first digits of the PC value are always 0.

It is important to note that when you save R15 with str/stm, it is possible to save the current instruction address value by 8 bytes, or to save the current instruction address value plus 12 bytes. Which way depends on the specific design of the chip. For the user, try to avoid using the STR/STM directive to save R15 values.
When a value is written to the R15 successfully, the program jumps to that address to execute. Since arm directives are word-aligned, the values written to R15 should meet bits[1:0] as 0b00, specifically requiring arm versions to be different:
* * for ARM3 and lower versions, the address value written to R15 bits[1:0] is ignored, that is, the address value written to R15 will be done with 0xFFFF FFFC.
* * for ARM4 and later versions, the program must ensure that the address value written to R15 bits[1:0] is 0b00, otherwise unpredictable consequences will occur.
For the thumb instruction set, the command is aligned and the processor ignores bit[0].

Program Status Register

The CPSR (current program State Register) is accessed in any processor mode. It contains the conditional flag bit, interrupt stop bit, current processor mode flag, and some other control and status bits.

。 When a particular abnormal interrupt occurs, this register is used to hold the contents of the current program State Register There is a dedicated physical state register in each processor mode called SPSR (Backup program status register).

You can use SPSR to recover CPSR when an abnormal interrupt exits. because user mode and system mode are not exceptions

interrupt mode, so he has no spsr. When a user accesses SPSR in user mode or system mode, unpredictable consequences will occur.
The CPSR format is shown below. The SPSR and CPSR formats are the same.

31 30 29 28 27 26 7 6 5 4 3 2 1 0
N Z C V Q DNM (RAZ) I F T M4 M3 M2 M1 M0

Conditional flag Bit * * *
The value of the n--standard set to the bit[31] of the result of the current instruction operation. When two represented signed integer operations, n=1 indicates that the result of the operation is negative, and n=0 indicates that the result is a positive book or zero.

Z--z=1 indicates that the result of the operation is zero, and the z=0 indicates that the result of the operation is nonzero. For CMP directives, z=1 represents the same size as the two numbers that are compared.

c--The following four scenarios to discuss how C is set up:
In the addition instruction (including the comparison instruction CMP), when the result produces a carry, then the C=1, which indicates that the unsigned operation occurred overflow; other conditions c=0.
In the subtraction instruction (including the subtraction instruction CMP), when dislocation occurs in the operation, C=0, which indicates an overflow of unsigned operands, and c=1 in other cases.
For non-alkali operation instructions that contain a shift operation, C contains the numeric value of the last overflow bit
For other non-additive operations directives, the value of the C-bit is not usually affected
v--for the addition and subtraction operation instruction, when the operand and the result of the operation are the signed number represented by the complement of the binary, the v=1 indicates that the symbol is overflow, and usually other directives do not affect the V-bit.

Q Identification Bit * * *
In arm V5 's e-series processors, CPSR's bit[27] is called the Q identification bit and is primarily used to indicate whether an enhanced DSP instruction has overflowed. The same SPSR bit[27] bit is also known as the Q identity bit, which is used in the exception

The q identification bit in the CPSR is saved and restored when the fault occurs.
In previous versions of Arm V5 and in the non-e-series processors of Arm V5, the Q identity bit was not defined.

Control bits in the CPSR * * *

The lower eight bits of CPSR I, F, T, m[4:0] are collectively referred to as control bits. These bits change when an abnormal interrupt occurs. In the privileged processor mode, the software can modify these control bits.

* * Interrupt Disable bit: Disable IRQ interrupt when I=1, disable Fiq interrupt when f=1

**t control bit: The T control bit is used to control the state of the instruction execution, that is, whether this instruction is an arm instruction or a thumb instruction. For ARM V4 with a higher version of the T-series ARM processor, the T-control bit has the following meanings:
T=0 means executing arm instructions
T=1 indicates that the thumb command is executed
For ARM V5 and later non-T series processors, the T control bit has the following meanings
T=0 means executing arm instructions
T=1 means forcing the next executed instruction to produce an indeterminate instruction interrupt

M Control bit * * *
The M control bit controls the processor mode, with the following meanings:

M[4:0] Processor mode accessible registers
10000 User PC,R14~R0,CPSR
10001 FIQ Pc,r14_fiq-r8_fiq,r7~r0,cpsr,spsr_fiq
10010 IRQ PC,R14_IRQ-R13_IRQ,R12~R0,CPSR,SPSR_IRQ
10011 SUPERVISOR Pc,r14_svc-r13_svc,r12~r0,cpsr,spsr_svc
10111 ABORT Pc,r14_abt-r13_abt,r12~r0,cpsr,spsr_abt
11011 Undefineed Pc,r14_und-r8_und,r12~r0,cpsr,spsr_und
11111 SYSTEM PC,R14-R0,CPSR (ARM V4 and later)

Other bits in CPSR * * *

These bits are used for future expansion. The application software does not manipulate these bits.

Registers for ARM processors