Registers included with 32-bit Intel CPUs

4 Data registers (EAX, EBX, ECX, and edx)
2 variable address and pointer registers (ESI and EDI) 2 pointer registers (ESP and EBP)
6 segment Registers (ES, CS, SS, DS, FS and GS)
1 instruction Pointer Register (EIP) 1 flag Register (EFLAGS)

1. Data register

Data registers are primarily used to store information such as operands and results of operations, thus saving the time required to consume the bus and access memory for the number of read operations.

The 32-bit CPU has 4 general-purpose registers of 32-bit eax, EBX, ECX, and edx. Access to low 16-bit data does not affect data that is 16 bits high. These
The low 16-bit registers are named: AX, BX, CX, and DX, which match the registers in the previous CPU.

4 16-bit registers can be divided into 8 independent 8-bit registers (Ax:ah-al, BX:BH-BL, CX:CH-CL, DX:DH-DL), each sent
The register has its own name and can be accessed independently. Programmers can use this "can-do" feature of data registers to handle word/word flexibly
Information about the section.

Registers Ax and Al are often called accumulators (accumulator), and operations with accumulators may take less time. Accumulators can be used to multiply,
In addition, input/output and other operations, they are very high frequency of use;
The register BX is called the base register. It can be used as a memory pointer;
The register CX is called the Count register. It is used to control the number of loops during loop and string manipulation.
, when moving multiple bits, it is necessary to use CL to indicate the number of displaced bits;
The register DX is called the data register. It can participate in the operation as the default operand when the multiply, divide operation is performed, or
The port address that can be used to hold I/O.


In 16-bit CPUs, AX, BX, CX, and DX cannot hold the address of a storage unit as a base address and a variable address register, but in a 32-bit CPU, its 32-bit
Registers eax, EBX, ECX, and edx can not only transmit data, hold data, save arithmetic logic results, but also act as pointer registers.
Therefore, these 32-bit registers are more versatile.

2. Variable address register

The 32-bit CPU has 2 32-bit general-purpose registers ESI and EDI. Its low 16 bits correspond to the SI and di in the previous CPU, and access to low 16 bits of data does not affect
High 16 bits of data.

Registers esi, EDI, Si, and di are referred to as the variable-address registers (Index register), which are mainly used to hold the offset of the storage unit within the segment,
They can be used to address a variety of memory operations, providing convenient access to storage units in different addresses.

The variable address register is not divisible into 8-bit registers. As a general register, the operands and results of arithmetic logic operations can also be stored.

They can be used as a general memory pointer. During the execution of the string manipulation instructions, they have specific requirements and also have a special
Features.

3. Pointer register

The 32-bit CPU has 2 32-bit general-purpose registers EBP and esp. The lower 16 bits correspond to the SBP and SP in the previous CPU, and access to the low 16-bit data
16-bit higher data.

Register EBP, ESP, BP, and SP, called the Pointer Register (Pointer register), are primarily used to store the offset of the storage unit within the stack,
They can be used to address a variety of memory operations, providing convenient access to storage units in different addresses.

The pointer register is not divisible into 8-bit registers. As a general register, the operands and results of arithmetic logic operations can also be stored.

They are primarily used to access storage units within the stack and provide for:

BP is the base pointer (base Pointer) register, which can directly access the data in the stack;
The SP is a stack-Pointer register that can only access the top of the stack.

4, Segment Register

Segment registers are set according to the management mode of memory fragmentation. The physical address of the memory unit is combined with the value of the segment register and an offset
So that the two less digits can be combined into a memory address that accesses the larger physical space.

Segment registers inside the CPU:

cs--Code Segment Register, whose value is the segment value of the code snippet;
ds--Data Segment Register, whose value is the segment value of the data segment;
es--Additional segment Register (Extra Segment register), whose value is the segment value of the additional data segment;
The ss--stack segment register (stack Segment register), whose value is the segment value of the stack segment;
fs--Additional segment Register (Extra Segment register), whose value is the segment value of the additional data segment;
The gs--additional segment register (Extra Segment register), whose value is the segment value of the additional data segment.

In a 16-bit CPU system, it has only 4 segment registers, so the program can be accessed directly at most 4 of the segments being used at any given time, and in 32-bit
In a microcomputer system, it has 6 segment registers, so the program developed in this environment can access up to 6 segments at the same time.

32-bit CPUs have two different ways of working: real-mode and protection. In each of these ways, the function of the segment register is different. The relevant provisions Jane
The single description is as follows:

Real mode: The first 4 segment registers CS, DS, ES, and SS have exactly the same meaning as the corresponding segment registers in the previous CPU, the logic of the memory unit
The address is still in the form of "segment value: Offset". To access data within a memory segment, the offset of the segment register and the storage unit must be used.
Protection mode: In this way, the situation is much more complicated, the loading segment register is no longer a segment value, but a value called "Selector".

5. Instruction Pointer Register

The 32-bit CPU expands the instruction pointer to 32 bits, and the lower 16 bits of the EIP,EIP are the same as the IP in the previous CPU.

The instruction Pointer Eip, IP (instruction Pointer) is the offset of the code snippet that holds the next instruction to be executed. In the function with prefetch instructions
System, the next instruction to be executed is usually pre-fetching to the instruction queue, unless a transfer occurs. So, in understanding their function
, the presence of an instruction queue is not considered.

In real mode, since the maximum range for each segment is 64K, the high 16 bits in the EIP are definitely 0, at this time, the equivalent of only using its low 16-bit
IP to reflect the order in which the instructions in the program are executed.

6. Flag Register

First, the result of the operation of the flag
1. Carry Mark CF (Carry flag)
The carry flag CF is mainly used to reflect whether the operation produces rounding or borrow. If the highest bit of the result of the operation produces a carry or borrow, its value is 1, otherwise its value is 0.

The use of this flag bit is: the addition and subtraction of the number of characters (bytes), the size of the unsigned number comparison operation, the shift operation, the word (byte) between the shift, specifically change the CF value of the instructions.

2, Parity Mark PF (Parity flag)
The parity Mark PF is used to reflect the parity of the number of "1" in the result of the operation. If the number of "1" is even, the value of PF is 1, otherwise its value is 0.

The PF can be used for parity checking, or for generating parity bits. In the process of data transmission, in order to provide the reliability of the transmission, if the use of parity method, you can use the flag bit.

3. Auxiliary carry sign AF (auxiliary Carry flag)
The value of the secondary carry Flag AF is set to 1 if the following occurs, otherwise its value is 0:

(1), in the word operation, the occurrence of low-byte high-byte rounding or borrow;
(2), when the byte operation, occurs when the low 4-bit to high 4-bit carry or borrow.

For the above 6 operation result flag bits, in the general programming case, the use frequency of the flag bit CF, ZF, SF and of is higher, while the use frequency of the flag bit PF and AF is low.

4, 0 Mark ZF (Zero flag)
The 0 symbol ZF is used to reflect whether the result of the operation is 0. If the result of the operation is 0, its value is 1, otherwise its value is 0. This flag bit can be used when judging whether the result of the operation is 0 o'clock.

5. Symbol SF (sign flag)
The symbolic symbol SF is used to reflect the symbolic bit of the result of the operation, which is the same as the highest bit of the result. In the microcomputer system, the signed number uses the complement notation, so the SF also reflects the positive and negative sign of the result of the operation. When the result of the operation is positive, the SF value is 0, otherwise its value is 1.

6. Overflow mark of (Overflow flag)
The overflow flag of is used to reflect whether the signed number plus minus operation results in overflow. If the result of the operation exceeds the range that can be represented by the current number of operations, it is called overflow, and the value of of is set to 1, otherwise the value of of is cleared to 0.

"Overflow" and "carry" are two different meanings of the concept, do not confuse. If you're not sure, check out the relevant chapters in the principles of computer composition course.

Second, the status control mark bit
The status control flag bits are used to control CPU operation, and they have to be changed by special instructions.

1. Tracking Mark TF (TRAP flag)
When the trace flag TF is set to 1 o'clock, the CPU goes into single step execution, that is, each execution of an instruction, resulting in a single step interrupt request. This method is mainly used for program debugging.

There is no specific instruction in the instruction system to change the value of the flag bit TF, but the programmer can use other methods to change its value.

2. Interrupt Allow flag if (interrupt-enable flag)
The interrupt allow flag if is used to determine whether the CPU responds to an interrupt request made by a masked interrupt outside the CPU. However, regardless of the value of the flag, the CPU must respond to an interrupt request from an unshielded interrupt outside the CPU, as well as an interrupt request that is generated internally by the CPU. Specific provisions are as follows:

(1), when if=1, the CPU can respond to the interrupt request of a masked interrupt outside the CPU;

(2) When if=0, the CPU does not respond to interrupt requests made by a masked interrupt outside the CPU.

The instruction system of the CPU also has special instructions to change the value of the flag bit if.

3. Direction Mark DF (Direction flag)
The direction flag DF is used to determine the direction in which the pointer register adjusts when the string operation instruction executes. The specific provisions are given in section 5th 2.11--string manipulation instructions. In the instruction system of microcomputer, a special instruction is provided to change the value of the flag bit DF.

Three, 32-bit flag register increased flag bit
1. I/O privilege flag iopl (I/O Privilege level)
The I/O privilege flag is represented by a two-bit bits, also known as an I/O privilege level field. This field specifies the privilege level that requires the execution of I/O directives. If the current privilege level is less than or equal to the value of IOPL, then the I/O instruction executes, or a protection exception occurs.

2. Nested task flag NT (Nested Task)
Nested task Flags NT is used to control the execution of interrupt return instruction Iret. Specific provisions are as follows:

(1), when nt=0, restore EFlags, CS, and EIP with the values stored in the stack, perform the normal interrupt return operation;

(2), when the nt=1, through the task conversion to achieve interrupt return.

3. Restart flag RF (Restart flag)
Restart flag The RF is used to control whether the debug failure is accepted. Rule: When Rf=0, said "accept" debug failure, otherwise refused. After a successful execution of an instruction, the processor set the RF to 0, and when it accepts a non-debug fault, the processor will set it to 1.

4, virtual 8086-way flag VM (virtual 8086 mode)
If the value of this flag is 1, the processor is in the virtual 8086 mode of operation, otherwise, the processor is in a general protection mode of operation.

Registers included with 32-bit Intel CPUs