Relationship between ARM condition codes and CPSR flag

In the arm system, all arm commands can be executed with conditions and some condition execution codes are set. However, these condition codes correspond to the Z, C, N, V flag bits in CPSR: l 0000 = eq-Z set (equal)L 0001 = ne-Z clear (not equal)L 0010 = cs-C set (unsigned higher or same)L 0011 = Cc-C clear (unsigned lower)L 0100 = mi-N set (negative)L 0101 = pl-N clear (positive or zero)L 0110 = vs-V set (overflow)L 0111 = VC-V clear (No overflow)L 1000 = Hi-C set and Z clear (unsigned higher)L 1001 = LS-C clear or Z set (unsigned lower or same)L 1010 = Ge-N set and V set, or N clear and V clear (greater or equal)L 1011 = lt-N set and V clear, or N clear and V set (less)L 1100 = gt-Z clear, and either N set and V set, or N clear and V clear (greater)L 1101 = le-Z set, or N set and V clear, or N clear and V set (less than or equal)L 1110 = Al-alwaysL 1111 = Nv-NeverHow can we understand these settings? Take 1001 = LS-C clear or Z set (unsigned lower or same) For example:Is why ls corresponds to C clear and Z set. Let's take a look at the following example: mov r0, # 5mov R1, # 6cmp r0, r1movls R2, R0; If R0 <R1 stores the small value in R2. in this example, the condition C = 0 and Z = 1 that can be correctly executed by movls is true. It is set through CMP. Let's see the CMP setting rules in reference manual: C flag: For a subtraction, including the comparison instruction CMP , C is set to 0 if the subtraction produced a borrow (that is, an unsigned underflow), and to 1 otherwise. Z flag: is set to 1 if the result of the instruction is zero (which often indicates an equal result from A comparison), and to 0 otherwise.This makes it easy to understand the correspondence between LS and flag. The following describes how to set the flag spaces so that we can deduce each example above. In either case, the new condition code flags (after the instruction has been executed) usually mean: N Is set to bit 31 of the result of the instruction. If this result is regarded as a two's Complement Signed integer, then n = 1 if the result is negative and n = 0 if it is positive or zero. Z Is set to 1 if the result of the instruction is zero (which often indicates an equal result from A comparison), and to 0 otherwise. C Is set in one of four ways: • For an addition, including the comparison instruction CEN , C is set to 1 if the addition Produced a carry (that is, an unsigned overflow), and to 0 otherwise. • For a subtraction, including the comparison instruction CMP , C is set to 0 if Subtraction produced a borrow (that is, an unsigned underflow), and to 1 otherwise. • For non-addition/subtractions that ineffecate a shift operation, C is set to the last bit Shifted out of the value by the shifter. • For other non-addition/subtractions, C is normally left unchanged (but see Individual instruction descriptions for any special cases ). V Is set in one of two ways: • For an addition or subtraction, V is set to 1 if signed overflow occurred, regarding Operands and result as two's complement signed integers. • For non-addition/subtractions, V is normally left unchanged (but see the individual Instruction descriptions for any special cases ).Let's take a look at the settings of the GT (signed greater) Flag:
CMP-5,-4; Subtraction is not equal to 0, is negative, and has off overflow, so n = 1, V = 1 CMP 6, 5; the value after subtraction is 1 (n = 0), positive and no overflow (V = 0)