Relationship between interrupt number and Chip Pin

I have never understood the cause of this interrupt number. I always thought it was a number defined by the interrupt controller, but I recently read it.
This is not the case only after the interruption control of S3C2440. 2440 of Interrupt Processing can only handle 32 interrupts, but there are and 58 interrupt numbers in the kernel.
Disconnect int4 ~ 7 share one bit of an interrupt control register, int8 ~ 23 is also one of the shared control registers. I'm curious, how does it differentiate these interruptions? It is also clear in the kernel code
The following code (2.6.13 ).

1. "
   Include/ASM-arm/arch-s3c2410/irqs. h
   "
2. .....
3. /* Interrupts generated from the external interrupts sources */
4. #
   Define
    
   Irq_eint4
   
   S3c2410_irq
   (
   32
   )
   
   /* 48 */
5. #
   Define
    
   Irq_eint5
   
   S3c2410_irq
   (
   33
   )
6. #
   Define
    
   Irq_eint6
   
   S3c2410_irq
   (
   34
   )
7. #
   Define
    
   Irq_eint7
   
   S3c2410_irq
   (
   35
   )
8. #
   Define
    
   Irq_eint8
   
   S3c2410_irq
   (
   36
   )
9. #
   Define
    
   Irq_eint9
   
   S3c2410_irq
   (
   37
   )
10. #
    Define
     
    Irq_eint10
    
    S3c2410_irq
    (
    38
    )
11. #
    Define
     
    Irq_eint11
    
    S3c2410_irq
    (
    39
    )
12. #
    Define
     
    Irq_eint12
    
    S3c2410_irq
    (
    40
    )
13. #
    Define
     
    Irq_eint13
    
    S3c2410_irq
    (
    41
    )
14. #
    Define
     
    Irq_eint14
    
    S3c2410_irq
    (
    42
    )
15. #
    Define
     
    Irq_eint15
    
    S3c2410_irq
    (
    43
    )
16. #
    Define
     
    Irq_eint16
    
    S3c2410_irq
    (
    44
    )
17. ....

After reading N for a long time, I found the reason:
During initialization, the interrupt source and interrupt number are mapped one by one in the relevant startup code, and then irq_desc is initialized. When the interrupt is executed
State and control register to convert, convert the corresponding interrupt source to the interrupt number, and then execute the Interrupt Routine. Here, we will analyze the 2440 process in a simple way:
The irq_handler macro in "arch/ARM/kernel/entry-armv.S" is dealing with interruptions, and the code is as follows:

1. /*
2. * Interrupt handling. preserves R7, R8, R9
3. */
4. .
   Macro
   
   Irq_handler
5. 1
   :
   Get_irqnr_and_base
    
   R0
   ,
   R6
   ,
   R5
   ,
   LR
   
   // Here, the interrupt source is converted into a macro of the corresponding interrupt number, and the interrupt number is placed in R0.
6. Movne
   
   R1
   ,
   SP
7. @
8. @
   Routine
    
   Called
   
   With
   
   R0
   =
   IRQ
   
   Number
   ,
   R1
   =
   Struct
   
   Pt_regs
   *
9. @
10. Adrne
    
    LR
    ,
    1
    B
11. BNE
    
    Asm_do_irq
12. // The execution is generally interrupted. The function prototype is arch/ARM/kernel/IRQ. C"
13. // Asmlinkage void asm_do_irq (unsigned int IRQ, struct pt_regs * regs)
14. // We can see that the required parameters include the interrupt number and the registers to be saved when the CPU is interrupted.
15.  
16. #
    Ifdef
     
    Config_smp
17. /*
18. * XXX
19. *
20. * This macro assumes that irqstat (R6) and base (R5) are
21. * Preserved from get_irqnr_and_base abve
22. */
23. Test_for_ipi
     
    R0
    ,
    R6
    ,
    R5
    ,
    LR
24. Movne
    
    R0
    ,
    SP
25. Adrne
    
    LR
    ,
    1
    B
26. BNE
    
    Do_ipi
    
    // Internal CPU interruption or exception
27. #
    Endif
28.  
29. .
    Endm

The conversion macro get_irqnr_and_base from the interrupt source to the interrupt number should be analyzed here:
Defined in the include/ASM/ARCH/entry-macro.S:

1. .
   Macro
   
   Get_irqnr_and_base
   ,
   Irqnr
   ,
   Irqstat
   ,
   Base
   ,
   TMP
2. // Irqnr: used to store the last interrupt number, that is, the R0 passed above
3. // Irqstat: used to store the interrupted state, that is, the preceding R6
4. // Base: This is not used in this macro.
5. // TMP: This is used to store the basic address of the interrupt controller,
6. // When obtaining the value of each control register, the corresponding value is added based on the address.
7. MoV
   /
   TMP
   ,#
   S3c24xx_va_irq
    
   // Obtain the basic address of the interrupt controller (virtual address)
8. LDR
   /
   Irqnr
   ,
   [
   /
   TMP
   ,#
   0x14
    
   ]
   @
   Get
   
   IRQ
   
   No
9. 30000
   :
10. TEQ
    /
    Irqnr
    ,#
    4
11. Teqne
    /
    Irqnr
    ,#
    5
12. Beq
    
    1002
    F
    @
    External
     
    IRQ
    
    Reg
13. .....
14. // Here is the eint4 ~ Ing of the interrupt Number of eint23,
15. // Rq_eint4 is a basic number, that is, the number is disconnected from the previous interrupt number, during which the interrupt number is reserved for devices in other bus.
16. // The subsequent interrupt number is constantly + 1 on the basis of this number. Here is its code.
17. MoV
    /
    Irqnr
    ,#
    Irq_eint4
    @
    Start
     
    Extint
    
    Nos
18. MoV
    /
    Irqstat
    ,/
    Irqstat
    ,
    LSR
    #
    4
    @
    Ignore
     
    Bottom
    
    4
    
    Bits
19. 10021
    :
20. Movs
    /
    Irqstat
    ,/
    Irqstat
    ,
    LSR
    #
    1
21. // This is based on the interrupted state and then determines whether the interrupted has occurred.
22. BCS
    
    1004
    F
23. Add
    /
    Irqnr
    ,/
    Irqnr
    ,#
    1
24. CMP
    /
    Irqnr
    ,#
    Irq_eint23
25. Ble
    
    10021
    B
26. .....

Here we have completed the correspondence between the interrupt pin and the interrupt number !!! However, the ing between each architecture and the interrupt controller should be different. This is only true for the S3C2440.
Here the interruption is completed.