Relationship between virtual addresses and physical addresses in Nboot and Eboot

When you look at Nboot and Eboot source programs, you will find two types of addresses: Virtual Address and physical address. virtual address is the address you use in the program, the physical address is the actual address in RAM. In Bootloader, you can directly use the physical address. However, when WinCE is started, you can only use the virtual address.

In Bootloader, a macro-defined function is usually used to convert each other, for example:

# Define VIRTUAL_TO_PHYSICAL (va)-VA_BASE + _ RAM_STARTADDRESS)
# Define VIRTUAL_TO_PHYSICAL (va)-VA_BASE + _ RAM_STARTADDRESS)

The parameter is defined as follows: (an example based on S3C2410A)

# Define _ RAM_STARTADDRESS 0x30000000
# Define VA_BASE 0x8C000000 // defined in OEMAddressTable
# Define _ RAM_STARTADDRESS 0x30000000
# Define VA_BASE 0x8C000000 // defined in OEMAddressTable

_ RAM_STARTADDRESS is the actual physical start address of RAM.

Va_base is defined in oemaddresstable. This oemaddresstable is defined in map in wince4.2. A (located in $ (_ winceroot)/platform/userplatform/kernel/hal/ARM/). In wince5.0, It is defined in oemaddrtab_cfg.inc (located at $ (_ winceroot) /platform/userplatform/src/INC /).

For example:

Physical address size

 

Oemaddresstable:

Dd 0x8c000000 0x30000000 64 m

Dd 0 0 0

 

Note:

The ram of S3C2410 is defined as the address starting from 0x30000000;
The virtual address is not defined as needed. It must be 0x80000000-0x9fffffff in wince. In fact, WinCE creates two sets of virtual address space, one is 0x80000000-0x9fffffff, and the other is cache enabled. The other is 0xa0000000 --- 0 xbfffffff, Which is cache disabled.
If the space we access is only a piece of memory space (for example, SDRAM), we can use the cache enabled space to access the data quickly, because the data is stored in the cache.

If the space we access is a peripheral address, we need to use the space of cached disabled for access so that the CPU and Peripherals can be synchronized.

 

 

The following describes the physical address allocation of the memory controller of the S3C2410 chip:

 

Let's look at an example of g_oalAddressTable:

; Export Definition

EXPORT g_oalAddressTable [DATA]

;------------------------------------------------------------------------------
;
; TABLE FORMAT
; Cached address, physical address, size
;------------------------------------------------------------------------------

G_oalAddressTable

DCD 0x80000000, 0x30000000, 64; 64 mb dram bank 6
DCD 0x84000000, 0x10000000, 32; PCMCIA/pccard bank 2
DCD 0x86000000, 0x18000000, 32; netcard bank 3
DCD 0x88000000, 0x00000000, 96; 96 mb nor Flash
DCD 0x90800000, 0x48000000, 1; Memory control register
DCD 0x90900000, 0x49000000, 1; USB Host register
DCD 0x90A00000, 0x4A000000, 1; Interrupt Control register
DCD 0x90B00000, 0x4B000000, 1; DMA control register
DCD 0x90C00000, 0x4C000000, 1; Clock & Power register
DCD 0x90D00000, 0x4D000000, 1; LCD control register
DCD 0x90E00000, 0x4E000000, 1; NAND flash control register
DCD 0x91000000, 0x50000000, 1; UART control register
DCD 0x91100000, 0x51000000, 1; PWM timer register
DCD 0x91200000, 0x52000000, 1; USB device register
DCD 0x91300000, 0x53000000, 1; Watchdog Timer register
DCD 0x91400000, 0x54000000, 1; IIC control register
DCD 0x91500000, 0x55000000, 1; IIS control register
DCD 0x91600000, 0x56000000, 1; I/O Port register
DCD 0x91700000, Zero x 57000000, 1; RTC control register
DCD 0x91800000, 0x58000000, 1; A/D convert register
DCD 0x91900000, 0x59000000, 1; SPI register
DCD 0x91a00000, 0x5a000000, 1; SD interface register
0x92000000, 0x00000000, 32; original location of 32 MB of nor flash
DCD 0x94000000, 0x34000000,192; 192 MB Bank 6 & 7-extended RAM
DCD 0x00000000, 0x00000000, 0; end of table
; Export Definition

Export g_oaladdresstable [Data]

;------------------------------------------------------------------------------
;
; TABLE FORMAT
; Cached address, physical address, size
;------------------------------------------------------------------------------

G_oalAddressTable

DCD 0x80000000, 0x30000000, 64; 64 mb dram bank 6
DCD 0x84000000, 0x10000000, 32; PCMCIA/pccard bank 2
DCD 0x86000000, 0x18000000, 32; netcard bank 3
DCD 0x88000000, 0x00000000, 96; 96 mb nor Flash
DCD 0x90800000, 0x48000000, 1; memory control register
DCD 0x90900000, 0x49000000, 1; USB Host register
DCD 0x90a00000, 0x4a000000, 1; interrupt control register
DCD 0x90b00000, 0x4b000000, 1; DMA control register
DCD 0x90c00000, 0x4c000000, 1; clock & Power register
DCD 0x90D00000, 0x4D000000, 1; LCD control register
DCD 0x90E00000, 0x4E000000, 1; NAND flash control register
DCD 0x91000000, 0x50000000, 1; UART control register
DCD 0x91100000, 0x51000000, 1; PWM timer register
DCD 0x91200000, 0x52000000, 1; USB device register
DCD 0x91300000, 0x53000000, 1; Watchdog Timer register
DCD 0x91400000, 0x54000000, 1; IIC control register
DCD 0x91500000, 0x55000000, 1; IIS control register
DCD 0x91600000, 0x56000000, 1; I/O Port register
DCD 0x91700000, Zero x 57000000, 1; RTC control register
DCD 0x91800000, 0x58000000, 1; A/D convert register
DCD 0x91900000, 0x59000000, 1; SPI register
DCD 0x91a00000, 0x5a000000, 1; SD interface register
0x92000000, 0x00000000, 32; original location of 32 MB of nor flash
DCD 0x94000000, 0x34000000,192; 192 MB Bank 6 & 7-extended RAM
DCD 0x00000000, 0x00000000, 0; end of table

 

According to the internal memory controller design of the S3C2410 chip, the physical address space of the system from 0x48000000 to 0x5fffffff is named SFr (special function register) in-chip peripheral registers (including control registers, status registers, data buffers, etc.), from the table above, we can see that there are USB, LCD and other peripherals.

The physical address ranges from 0x00000000 to 0x3fffffff. This 1 GB is divided into eight banks, each having a physical address space of MB. Only bank6 and bank7 support the ram storage type.

The physical address 0x30000000 to 0x3fffffff is used by physical RAM in a MB area, which is actually full of the MongoDB memory controller's bank6 and bank7. As shown in the table above, although the physical address is continuous, the virtual address can be discontinuous, that is, divided into 64 MB and MB.

The physical address 0x00000000 to 0x05fffffff is occupied by nor flash storage, and its total capacity is 96 MB.

The bank2 of the storage controller is occupied by a 32 MB memory PC Card peripherals.

The storage controller bank3 is occupied by an external Ethernet controller chip.

This article from the csdn blog, reproduced please indicate the source: http://blog.csdn.net/formerman/archive/2009/07/16/4354626.aspx