Repost the priority of the case statement

For such a combined logic circuit [email protected] (x) Case (x) x1: X2 :...... Endcase if the branch item contains all the values of variable X and does not overlap with each other, there is no need to use a comprehensive command in this case. (1) Some books in "// synthesis parallel_case" are used to introduce case statements (for example, the comprehensive and practical tutorial of OpenGL) in this example, the "case statement" in the Tilde-HDL semantics indicates the priority of case Branch selection. The case expression is first compared with the first branch, and so on ......" However, the experiment in Quartus shows that when the branch item contains all values of the variable X and does not overlap with each other, the branch options of the case statement have the same priority, in this case, the use of the comprehensive command "// synthesis parallel_case" does not work. If two branch options overlap, the priority sequence implied by case takes effect. The priority of the previous branch items is high, and Quartus generates the following warning during compilation: warning (10935): maid/casez warning at DDD. V (380): casex/casez item expression overlaps with a previous casex/casez item expression reminds you that branch items overlap. In this case, if the "// synthesis parallel_case" command is not used, overlapping branch items will be integrated according to the principle of "the previous branch item has a higher priority. If the "// synthesis parallel_case" command is used, we can divide the following subsets: A1 (x1, but not other), A2 (X2, but not others ), in this way, for the subset A1, the statement is executed in strict accordance with the Statement in X1:, for the subset A2, the statement in strict accordance with X2:, and so on. For other situations that cannot be divided into any subset, that is, overlapping parts, it is regarded as an impossible situation, or a situation that does not care about. In this case, how to combine it is conducive to simplifying the circuit is integrated. Therefore, "// synthesis parallel_case" is useful for simplifying the circuit. This command can be used to simplify the circuit as long as the designer determines that the overlap does not occur. At this time, Quartus will give a warning: Warning (10935): maid/casez warning at least log1.v (15 ): casex/casez item expression overlaps with a previous casex/casez item expression warning (10935): OpenGL HDL casex/casez warning at least log1.v (16 ): casex/casez item expression overlaps with a previous casex/casez item expression warning (10209): Maid case statement warning at login log1.v (13): honored paralle Rochelle case synthesis Attribute-differences between design synthesis and simulation may occur (2) "// synthesis full_case" in the preceding logic circuits, if the branch item does not contain all the situations, it will be integrated into a trigger, so you can use default to avoid this situation. If you don't care about the situation, you just need to assign a value at will, but the price of this random assignment is the logical resource. If "// synthesis full_case" is used, the synthesizer automatically assigns values to unlisted cases, and the value assigned by it helps reduce the consumption of logical resources. As for the reason, I think we can use the example of simplification of the Kano diagram to explain that for situations that we don't care about, we should just give it an X. During simplification, it can be used as 0, it can also be used as 1. it is obviously better than giving it a 0 or 1. This is why we use "// synthesis full_case.

Repost the priority of the case statement