[Reprint] Memory literacy

https://www.cnblogs.com/jintianfree/archive/2010/03/16/1687540.html#3841218

A quick supplement to some of the basics of memory, primarily to understand DPDK, is not involved too deeply.

Brief introduction

RAM random access memory, random access refers to the contents of the storage unit can be withdrawn or deposited as needed, and the speed of access is independent of the location of the storage unit.

RAM is divided into SRAM (static random access memory) and DRAM (dynamic random access memory),

SRAM has complex structure, small unit area capacity and fast access speed.

The DRAM structure is simple, the unit area capacity is many, the storage speed is slow.

Because of its simple structure, the stored charge disappears over time, so it requires a recharge (refresh) action to keep the stored data.

SRAM is suitable for registers and CPU caches. DRAM is suitable for caches and other hardware devices

Main memory (usually referred to as the RAM) structure hierarchy

Main memory dram from large to small, from the top down can be divided into the following:

Channel > DIMM > Rank > Chip > Bank > Row/column

Correspondence between main memory from channel to Chip

Chip split down

Bank down is a storage unit, horizontal row, vertical column. There is a row buffer below each column to cache the read-out data.

Channel

In the past, memory speeds were able to keep up with the processor ' s requirements. However, when we reached the point where the processor's ability to process data is accelerating faster than current mem Ory Technologies could support, memory became a major limitation in system performance. Simply put, memory speeds could no longer keep up with advances in processor speeds and data throughput. A new method to get more data to the processor in mainstream computers is needed–without relying solely on memory speed .

Intel and many system architects decided that the solution is to add a second Channelof memory–called the "dual channel "Memory layout.

A processor in a computer was like the engine of a car. A car needs gasoline to fuel its engine. Similarly, a computer processor needs memory storage to process its data. Data (in bits which is zeros and ones) must is stored in memory first, before being delivered to the processor. When more data can is delivered to the processor via memory at faster speeds, the processor can manipulate instructions an D data more efficiently and ultimately, the requested task can is accomplished in less time.

To illustrate the difference between Single-and dual-channel memory, let's extend the analogy above. Data is filled into a funnel (memory); The funnel then "channels" the data through it pipe to the processor ' s input:in this illustration, Single-channel Memor Y is like a funnel this feeds data to the processor engine through a single pipe. Data is transferred.

Dual-channel Memory utilizes-funnels (and thus-pipes) to feed data to the processor, thereby being able to deliver Twice the data of the single funnel. With and funnels or channels, data is transferred-bits at a time. The process works the same is the "emptied" from the processor by reversing the flow of data. To prevent the funnel from being over-filled and data or to reverse the flow of data through the funnel, there is a "Traf FIC "controller shown as a valve on the funnel ' s pipe. In computers, there are a special chip called the "Memory Controller" that handles all data transfers involving the memory Modules and the processor.

The memory Controller manages all movement of data between the processor and the memory modules. Data is sent to the Memory Controller (which are part of a computer motherboard ' s "chipset"). The memory Controller is like a traffic signal this regulates data transfer either to Memory modules for storage, or to th e processor for data manipulation or "crunching". Graphically, this architecture is pictured below:

Data moves through the funnel ' s pipe in one Direction at a time (just like a one-lane bridge that can being used in both Dir Ections, but only one car can cross it at a time). The memory controller acts like a traffic signal that directs the movement of data across the memory channel. For example, data arriving to the memory Controller are first stored in the memory modules (2), then is re-read (3) and Fin Ally transferred to the processor (4). On a typical motherboard, these same components can be easily identified:

Dimm

The DRAM chip is packaged in a memory module, which is plugged into the expansion slot of the motherboard. The common packaging is a 168-pin dual-inline memory module (Dual inline memory Module,dimm) that transmits data to the storage controller and from the storage controller in 64-bit blocks. The DIMM is developed in a single inline memory Module,simm, and SIMM transmits data in blocks of 32 bits.

Rank

The memory controller only allows the CPU to do a set of 64bits of data exchange with memory at a time, and this 64bit bandwidth is a rank, or 1rank = 64bits. Memory data reading and writing is a data width of 64bits each time, ECC memory increases the parity bit of 8bit, so ECC memory is 72bits.

Each memory particle (chip) on the memory, provides 4bit/8bit data, provides 4bit chip as X4, provides 8bit chip as X8, in order to form a rank, the memory needs to have 16 pieces of X4 chip or 8 x8 chip (without x4 and x8 chip mixing situation). Therefore, there are at least 8 memory particles on one DIMM, arranged on either side or both sides of the DIMM. Each side of the standard DIMM has enough space to accommodate the 9th chip, and the 9th chip is used to store 4bits or 8bits of ECC.

If the 9 chips of the 1 ECC DIMMs are on the same side of the DIMM, they are called single-sided, and if 9 chips are distributed on both sides of the DIMM, they are called double-sided.

DIMMs are also divided into Single-rank, Double-rank, Quad-rank (that is, 1R, 2R, and 4r,4r DIMMs that we often see on the lable of memory are typically used on the server).

Each rank of Double-rank can independently provide 64bit of data, the DIMM needs to have two chip selection signal, choose which rank, the selected rank, the data will go through the MUX output, or through the MUX input. The same Quad-rank has four rank, which can provide 4 sets of 64bit of data, which requires four chip selection signals to choose which rank to use.

The channel is for fast, multiple DIMMs can increase memory, what is multiple rank for? At present, I have only found the following description, is not yet certain.

Most companies prefer to use more chips, because this gives the DRAM more processing power and more areas in which to Stor E data. As of there is four types of rank:single or one layer, dual or both layers, quad or four layers and octal or eight Layers. The more layers, the more memory of the company can fit onto a chip. Commonly, consumers only find single-or dual-layer memory in their computers, while powerful server computers make use of The Quad-and Octal-layer ranked memory chips.

Original link:

Memory Literacy Basics

Resources:

The structure and principle of RAM, the channel of memory, Chip and bank

Intel Dual Channel DDR Memory Architecture

[Reprint] Memory literacy