[Reprint]synplify Use

The two most important indexes of comprehensive evaluation: whether the speed is fast and the area is small;
Synplify is a logic synthesis tool specifically for FPGA/CPLD;
The two most notable features of the synplify are the best and timing driven engines, which make the combined results more ideal in both speed and area;
Several versions of synplify use the same core, but the Synlify Pro features the most powerful;

The synplify synthesis process consists of three elements:
1. Compiling the HDL source code
Synplify translates the input HDL source code into a Boolean expression and optimizes the logical relationship;
2. Optimization of the results of the compilation
The logic optimization is used to eliminate redundant logic and multiplexing modules, which is based on the logic relationship and is independent of the specific device.
3. The optimization results are logically mapped and optimized at the structure level, and the net table is generated.
Synplify maps the generated logic relationships into FPGA stratigraphic modules and hardware primitives (primitive) to generate grid tables and optimize them.

Key features of Synplify Pro:
1. Support Hybrid Design: The source program in a project can contain both Verilog HDL code and VHDL code;
2.HDL Source Code Editor: You can edit the HDL source code directly in Synplify, its syntax correction function is powerful, there are syntax check and synthesis check two levels;
3.BEST (behavioral-level extraction technology): The Behavior-level extraction module is directly adapted to the FPGA underlying unit;
4.scope (Integrated constrained optimization environment): input and manage the constraints of design in spreadsheet form, so that users can easily, comprehensively and effectively design comprehensive constraints, the result is. sdc file
5.cross-probing: Easy to switch between code, view (RTL View and Technology view), emulation, report, and critical path
6.RTL View:synplify Pro uses best technology to reproduce the Register transfer level schematic after compiling the source code
7.technology view: Gate-level structural schematics that describe the hardware primitives (primitive) and underlying modules (embedded PLL RAM, etc.) that are designed with FPGA
Technology view is the result of a structural mapping of RTL views to specific devices
8.FSM Compiler: Finite state machine integrated tool
The essence of FSM EXPLOER/FSM VIEVER:FSM Explorer is the state machine optimization technique of timing driven;
FSM Viewer is a finite state machine observer;
9.TCL command interface, can greatly improve the work efficiency through TCL script;
10.resource sharing: Resource sharing to help reduce the physical area of your design footprint
11.retiming: Using register to split the combination logic, insert register balance delay in the combinational circuit to improve the working frequency of the chip;
Retiming technology is also one of the timing driven optimization techniques;
Pipelining:pipelining is mainly used in some algorithm paths, such as multiplier, adder, etc.
pipelining is local optimization and retiming is the whole optimization;
12. For specific manufacturers of the device provides a rich comprehensive attribute attributes;
13.probe: Probe, without changing the source of the premise of pulling out any signal to the output pin;
14.timing Analyst: Timing analysis expert, able to perform point-to-point path timing analysis;
15.automativ Gate Clock conversion:ic design and FPGA design of the gating clocks to synchronous clock conversion;

Synplify Interface:
1. Menu bar
2. Toolbars
3. Status Display bar: Shows the current status of the integrated device
4. Basic Operation Step button: organized in the Order of actual operation
5. Important Comprehensive Optimization parameter option settings: Focus on the parameters of the crime important in the process of comprehensive optimization, these parameters will directly determine the results of the synthesis
6. Project Management window: shows the engineering structure and resource files
7. project file Display window: Display project input file and synthesis result file
8. Message/tcl Script Display window
9. Integrated Results Observation window: Display the integrated results of the clock frequency, IO pin, register resources, LUT resources and select devices and other important information;

Synplify combined with Quartus:
1. Select Synplify Pro as the integrated tool in setting in Quartus, Quartus will automatically call Synplify Pro to complete the design process;
2. Enable Synplify Pro separately to complete the synthesis, output EDIF or VQM network table file, at this time quartus only complete the mapping and layout of the network table and other operations;

Synplify Pro's Operation steps:
1. Create a project
2. Adding and compiling source code
3.RTL and Technology observation
4. Use scope to design comprehensive constraints
5. Setting Comprehensive optimization parameters
6. Synthesis
7. Comprehensive post-analysis

Synplify Pro's scope comprehensive constraint options:
1 clock
2. Clock delay clocks to clock
3. Input/Output inputs/outputs
4. Register Registers
5. Multi-cycle path multi-cycle paths
6. Weakly constrained path false paths
7. Path Maximum delay Max_delay path
8. Constraint attribute attributes
9. Multi-location compilation compile points
10. Other
11.collections
12.IO Standard IO Standards

Tools for designing FSM in Synplify Pro:
The FSM compiler the FSM into a connection diagram of a similar state transfer diagram, and then re-encodes and optimizes the FSM to achieve better overall results.
FSM Explorer uses the results of the FSM compiler to select different coding methods for state machine code detection, so as to achieve the optimal performance of FSM coding;
FSM Viewer is a good tool for viewing FSM
Their role: To re-select the encoding method, to determine a more appropriate starting state, remove redundant logic and unreachable state;
When integrated, FSM compiler can be used to view the combined results of each state machine in log file;

The files generated later have the. srr. Tlg. SRS
. SRR: Engineering Report (important), with "PROJECT_NAME.SRR" command;
. TLG: Engineering Organizational Structure information file
. Srs:rtl View File

Use of TCL script files:

A designer can perform a synthesis in the form of batch commands, or it can perform multiple synthesis of the same design at once, trying different devices, different delay targets, and different constraints;
Project file PRJ, constraint file SDC is essentially written in Tcl script;
Methods of adding constraints: synplify scope, adding constraints to HDL;
Synplify the last compiled module/entity and architecture as a top-level design, so pull the top-level design file to the bottom of the design file list (otherwise it will only show the end HDL view in RTL view)
If resource sharing is selected during optimization, the maximum frequency is generally reduced, but resources are saved; It is recommended to save resources by selecting the design to meet the clock frequency requirements;
Pipelining is water, in the high-speed design if other measures can not reach the target frequency is best to select this;
Both the technology view and the RTL view are for HDL, which can be displayed before synthesis, and technology view is a hierarchical circuit based on the technology of the target device.
Time report (Timing reports): Preference summary part of the SRR, note that the synthesized time report is only an estimate, and the actual timing condition of the design relies heavily on the layout and routing tools;

[Reprint]synplify Use