Reproduced Vivado easily implements IP encapsulation

Vivado Easy Implementation IP Package

1 , create a new test project

Engineering Design method is inseparable from the project, the first step is often a new project, I will learn to engineering development methods, may be more efficient.

2 , using the wizard to complete IP Package

2.1 , start IP Wizards

The method is: Toolsàcreate and package ip...,1 shown.

　　　　　　　　　　Figure 1 Creating or packaging an IP

Click Create and Package IP ... command, the popup Wizard, shown in 2.

Figure 2 Creating and encapsulating IP wizards

Directly next, go to the next interface, shown in 3. Choose the type of operation, we are not new IP here, nor to package the current project, but to encapsulate the RUNLED_SRC folder into an IP, so select the 2nd item. NEXT.

Figure 3 Selecting the action type to encapsulate a specific directory

The next step to note, select the folder where you want to package the resources, I am here to pack the 3 files placed under the MY_IP/RUNLED_SRC, so select this path, 4 is shown.

Figure 4 folder where resources are to be packaged

Next, the wizard prompts you to develop a name and storage address for IP engineering, as shown in 5. This is the default name, the project is temporary, the IP package will disappear, and then re-establish the IP again.

Figure 5 Temporary project name, storage path

Next, Next is the last step, is a hint of information, you can see for yourself. Click Finish to finish the wizard.

Figure 6 Summary

2.2 , IP parameter Settings

Note that this has entered the Edit_ip_project project, which is the new project for packaging the IP core, and we have specified the name and path (see Figure 5).

After the packaging of the IP for some parameter configuration, such as suppliers, classification (the default is BASEIP, use to find our encapsulated IP in the classification) and other information, here is not detailed, when necessary, self-modification can be.

Figure 7 IP parameter settings

Next: Do not modify the properties, go directly to the last step (click Review and Package), click the Pack IP button in Figure 8 to start packing.

Figure 8 Start packing

After the package is complete, the Edit_ip_project project will automatically close and return to the test project we established.

3 , view IP Package Results

Locate Project Manageràip catalog under the Flow Navigator subform, click IP Catalog, the right side will pop up the IP Catalog subform, expand the Baseip directory, and discover that RUNLED_TOP_V1_0 has been successfully imported.

Here, the package has been completed, the topic to be described in this article has been completed.

------------------------------------------------------Split Line---------------------------------------------------------------

But because it is the first time to use, not too relieved, so test, then love to each section is testing, do not want to see can directly skip.

4 , Test

Create a block Design, add the RUNLED_TOP_V1_0, add the input and output port, and the final result 9 shows.

　　

Figure 9 Block Design

5 , adding constraints, synthesis, implementation, Generation bitstream

Constraint file:

#In  the following the XDC constraint is matched to the  Origanal ucf constraint, xdc above, ucf below # commented set_ property package_pin y9 [get_ports {iclk}]set_property iostandard lvcmos33  [get_ports {iclk}]  #NET  gclk          loc  = Y9   | IOSTANDARD=LVCMOS33;  #  "GCLK"  # bank 33 ,  vcco = 3.3v#set_property iostandard lvcmos33 [get_ports -filter {  IOBANK == 33 } ]SET_PROPERTY PACKAGE_PIN T22 [GET_PORTS {OLED[0] }]set_property iostandard lvcmos33 [get_ports {oled[0]}] #NET  LD0            LOC = T22  | IOSTANDARD=LVCMOS33;   #  "LD0" Set_property package_pin t21 [get_ports {oled[1]}]set_property iostandard lvcmos33  [Get_ports {oled[1]}] #NET  ld1           loc  = T21  | IOSTANDARD=LVCMOS33;  #  "LD1" Set_property package_pin  u22 [get_ports {oled[2]}]set_property iostandard lvcmos33 [get_ports {oled [2]}] #NET  LD2           LOC = U22   | iostandard=lvcmos33;  #  "LD2" set_property package_pin u21 [get_ports  {OLED[3]}]SET_PROPERTY IOSTANDARD LVCMOS33 [GET_PORTS {OLED[3]}] #NET  LD3            loc = u21  | iostandard= lvcmos33;  #  "LD3" set_property package_pin v22 [get_ports {oled[4]}]set_ Property iostaNDARD LVCMOS33 [GET_PORTS {OLED[4]}] #NET  LD4            LOC = V22  | IOSTANDARD=LVCMOS33;  #  "LD4" set_ Property iostandard lvcmos33 [get_ports {oled[5]}]set_property package_pin w22  [GET_PORTS {OLED[5]}] #NET  LD5            LOC = W22  | IOSTANDARD=LVCMOS33;  #  "LD5" set_property  Package_pin u19 [get_ports {oled[6]}]set_property iostandard lvcmos33 [get_ports  {OLED[6]}] #NET  ld6           loc =  U19  | IOSTANDARD=LVCMOS33;  #  "LD6" set_property iostandard  LVCMOS33 [GET_PORTS {OLED[7]}]SET_PROPERTY PACKAGE_PIN U14 [GET_PORTS {OLED[7]}] #NET  LD7   &NBsp;       loc = u14  | iostandard=lvcmos33;   #  "LD7"  # Bank 34, Vcco = Vadj#set_property IOSTANDARD  lvcmos18 [get_ports -filter { iobank == 34 } ]set_property  Iostandard lvcmos18 [get_ports {irst_n}]set_property package_pin p16 [get_ports  {irst_n}] #NET  btnc          loc = p16   | IOSTANDARD=LVCMOS18;  #  "BTNC"

Generate bitstream for board-level testing.

6 , Test

Use the Vivado built-in Hardware Manager wizard to write bitstream into the FPGA, and the running lights appear smoothly, ok!

Copyright Notice:

This paper is made by Bo Master "Cuter" published. Welcome reprint, but may not change the content of the blog post, nor for any profit purposes. The author's profile and copyright notice shall not be removed upon reprint. If there is misappropriation and does not indicate the copyright dispute caused by the source, the misappropriation is at their own risk.

Blog Official address:

chinaaet:http://blog.chinaaet.com/cuter521

EDN china:http://bbs.ednchina.com/blog_cuter521_356737.htm

Reproduced Vivado easily implements IP encapsulation