Reproduced Principle of CRC32 encryption algorithm

This article was reproduced from: http://blog.163.com/yucheng_xiao/blog/static/76600192201393092918776/

First, the basic principle

The CRC test principle is actually the addition of an R-bit binary test code (sequence) after a P-bit binary data sequence, thus constituting a binary sequence with a total length of n=p+r bits; There is a particular relationship between the code attached to the data sequence and the contents of the data series. This particular relationship can be compromised if one or some of the bits in the data series are incorrectly caused by interference, for reasons such as this. Therefore, by examining this relationship, we can test the correctness of the data.

Ii. several basic concepts

1. Frame Inspection sequence FCS (frame check Sequence): Redundant code added for error checking.

2, Polynomial Mode 2 operation: is actually bitwise XOR (Exclusive or) operation, that is, the same as 0, the difference is 1, that is, do not consider the carry, borrow binary addition and subtraction operations. such as: 10011011 + 11001010 = 01010001.

3, the generation of polynomial (generator polynomial): When the CRC test, the sender and receiver need to agree with a divisor, that is, to generate a polynomial, generally written as g (x). The highest and lowest bits of the generated polynomial must be 1. The common CRC code generation polynomial is:

Crc8=x8+x5+x4+1

Crc-ccitt=x16+x12+x5+1

Crc16=x16+x15+x5+1

Crc12=x12+x11+x3+x2+1

Crc32=x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x1+1

Each generated polynomial can correspond to a code, such as the CRC8 code: 100110001.

Third, the calculation of CRC test code

Set the information field to K bit and the check field to R bit, then the code word length is N (n=k+r). If the two parties have previously agreed to an R-Quadratic polynomial g (x), the CRC code:

V (x) =a (x) g (x) =xrm (x) +r (x)

Where: M (x) is the k-th information polynomial, R (x) is the R-1-check polynomial.

Here r (x) corresponding code is redundant code, added to the original information field after the formation of CRC code.

R (x) is calculated by adding R 0 after the K-bit information field, divided by the corresponding code sequence of g (x), the resulting remainder is R (x) corresponding to the code (should be R-1 bits; if not enough, and in the high 0).

Calculation example

The message to be sent is M = 1010001101, and the code that produces the polynomial corresponds to P = 110101,r=5. After M is added 5 0, then p modulo 2 division operation, the remainder R (x) corresponding code: 01110. So the actual data that needs to be sent is 101000110101110.

Figure 3.1

Iv.. Error detection

When the receiving party receives the data, with the received data to P (pre-agreed) Modulo 2 division, if the remainder is 0, the data transmission error is considered, if the remainder is not 0, it is considered that the data transmission errors, because do not know where the error occurred, and therefore can not be automatically corrected, the general practice is to discard the received data.

Five, several notes:

1, CRC is a common error-checking code, and can not be used for automatic error correction.

2, as long as the strict selection, and the use of a sufficient number of divisor P, then the probability of detection error is very small and small.

3, only with cyclic redundancy test CRC error detection technology can only do error-free acceptance (just very approximate think is error-free), and can not guarantee reliable transmission.

Six, mathematical reasoning although the above content has a clearer mathematical calculation process, in this section will give a more rigorous mathematical model to deepen the impression: consistent with the third section of the content 1. The information to be transmitted is K-bit, 6.1 shows 2. The data sequence m (x) to be transmitted is multiplied by the XR, where R is G ( x) of the highest times of the underworld.3. The polynomial to be obtainedXR m (x) divided by the agreed polynomial g (x)4. Ignore the "quotient" of the division result, take out the remaining number, andXRm (x) is added to form the sending sequence of the K+R bit, namely: M ' (x) = XRm (x) +r (x) Graph 6.1 CRC encoding process is as follows: The information code to be verified has k-bit, i.e.: M = (mk-1,mk-2,mk-3 ... M1,M0), the polynomial m (x) can be expressed as m (x) = mk-1xk-1+ mk-2xk-2 + ... m1x1+ m0x0------------------------------------------------------------------------type (1) With a polynomial g (x) the highest power R corresponding to the XR multiplied by M (x), the formula (2) XR m (x) =mk-1xk+r-1+ mk-2xk+r-2 + ... m1x1+r+ m0x0+r--------------------------------------------------------type (2) The XR m (x) modulo 2 divided by g (x), the polynomial quotient is a (x), the remainder is R (x), that is:A (x) g (x)= XR m (x) +r (x)-------------------------------------------------------------------------------------------------- ---(3) remainder polynomial R (x) can be expressed as r (x) =rr-1xr-1+ rr-2xr-2 + ... r1x1+ r0x0------------------------------------------------------------------------------------type (4) Formula (2) and formula (4) substituting (3) a (x) g (x) =mk-1xk+r-1+ mk-2xk+r-2 + ... m1x1+r+ m0x0+r + rr-1xr-1+ rr-2xr-2 + ... r1x1+ r0x0--------type (5) (5) The corresponding code group is k+r bit, i.e.: N = (mk-1+ mk-2 + ... M1+ M0 + rr-1+ rR-2 + ... R1+ R0)------------------------------------------------------------style (6) From M to n is the CRC encoding processmk-1+ mk-2 + ... M1+ M0 is a K-bit information code;rr-1+ rR-2 + ... R1+ R0 is an R-bit check code . At the receiving end, the received K+r code is divided by the same polynomial g (x), and according to the formula (3) The remainder is 0, then the received data information is correct, otherwise it is believed that the information generated in the transmission of the error. According to the formula (1) ~ formula (6), CRC encoding must be modulo 2 in addition to the operation, the CRC check bit is modulo 2 in addition to the remainder, if the remainder of the register with the number of registers, modulo 2 in addition to the XOR gate, then the general CRC serial circuit can be the same as the circuit shown in Figure 6.2 to achieve.    LFSR (Linear Feedback shift register) in the calculation process, the linear feedback shift register is a shift register: its input bit is a linear function of the previous state. 7.1 The blue box is the input bit, and the previous state is 0110, obviously, according to this diagram, the next state of the bit0 is Bit2,bit3, which is the function value of the argument.   Figure 7.1  So what can this function be? The binary algorithm is nothing more than a gate circuit, and the most commonly used linear function is XOR gate. The initialization value of the LFSR is called SeeD (the image point is the spark, such as 7.1 in 0110), and the operation of the Register is also determined, then the data flow generated by this shift register is also determined by the current state, on the other hand, because the shift register is limited and the number of bits is determined, So the data flow will inevitably go into a repeating cycle of cycles. Figure  7.2  Description: 1. Because of the uniqueness of the function, there is the uniqueness of the arrow. 2. Because of the limitations of the 4-bit LFSR, no matter how the data is formed, it is always inevitable to re-enter the 0110 state.   So this cycle must exist, as Buddha to Monkey King said, you can not run out of my five fingers mountain, of course, the actual situation is not only 5 states. Does the problem come up with a new question? How many fingers does the mountain have? The answer is this-as long as the feedback function is selected appropriately, the resulting random sequence will run a lot of "fingers" to return to the initial state, meaning that the cycle will be long. For a specific example, refer to Figure 7.3 Figure 7.3 a 4-bit Fibonacci LFSR with its state diagram. The xor gate provides feedback to the register, the shifts bits from left to right. The maximal sequence consists of every possible state except the ' 0000 ' state.
CRC (cyclic redundancy check) and LFSR have a very similar place, why do you say so? Continue the analysis, first look at a special structure of the LFRS. Galois Lfrs (Galois linear Feedback shift register) What is the Galois linear feedback shift register? Just to commemorate a mathematician, his name is Galois, know this is enough, the main thing is to master its structural characteristics, what is the characteristics of it? Figure 7.4 shows the 1> modular;2> XOR gate inserted in the internal;3> one-to-many LFSR figure 7.4 It is a rotating structure capable of producing the same output data stream as the traditional LFSR. There are several points of knowledge that need to be established before describing the structure's specific operational functions. 1> What is called a tap (taps) in the LFSR to affect the position of the next state bit is called a tap, in 7.1 is the position of Bit2, bit3, in Figure 7.4 is [16. 14.13. 11]. The corresponding polynomial isX +x +x+x+1, the following points in this polynomial are worth noting: A. The last 1 of the polynomial does not correspond to a single tap, it corresponds to the output bit (rightmost, i.e. X0) B. The first is directly connected. C. XOR gate output to the tap position, e.g. 14.13.11; One of the inputs is the previous position of the tap and the other input corresponds to the output bit. The 2> input bit, and the leftmost one in the output bit LFSR is the input bit, and the rightmost one is called the output bit. After the output bits and taps are different or operated, the data is moved to the right one bit. Summary of Operational laws (this is very important) 1. The output is 1 o'clock, there is an XOR gate position, the data is flipped to the right and down one position. There is no XOR gate position, and the number is shifted directly to the right down one position. 2. The output is 0 o'clock, with the position of the XOR gate, the data is not flipped but is moved directly to the right and down one position. There is no XOR gate position, and the number is shifted directly to the right down one position. since the output can only be 0 or 1, all operations should follow these two rules, as shown in 7.5 Figure 7.5 C Language Code implementation: Figure 7.6 illustrates: Please note that the difference between the hardware logic and the C language Logic C language implementation is to first put the data in the LFSR all right one bit, and then determine whether the previous output bit is 1 for 1 o'clock, the data at the tap is flipped, if 0 is unchanged.
Here is a problem, in the hardware circuit is the first flip and then the right to move 1 bits, and in the software language processing is the first right to move 1 bits, and then flipped in the corresponding position, and the actual end result is the same. The implementation of the process 7.7 is shown in Figure 7.7 Please compare the hardware circuit and the C language implementation of the same algorithm in the different processes of Figure 7.5 and figure 7.7. CRC Mode 2 operation and LFSR circuit implementation. The message to be sent is M = 1010001101, and the code that produces the polynomial corresponds to P = 110101,r=5. After M is added 5 0, then p modulo 2 division operation, the remainder R (x) corresponding code: 01110. So the actual data that needs to be sent is 101000110101110. The corresponding polynomial is 110101x5+ x4+ x2+1. Modulo 2 In addition to the operation process: Figure 7.8 Figure 7.6 illustrates: the number of steps on the left (such as the 6th step) represents the remainder of the divisor and polynomial modulus 2 minus. The number of steps on the right (such as step 8th) indicates that the highest bit of the remainder of the previous step (for example, step 6th) is 0 o'clock, moving the remainder one bit to the left, and bringing it into the dividend 1-bit accordingly.please compare with Figure 7.7 to analyze the actual circuit implementation process. 1th Step ———— 5th step: The divisor is moved into the LFSR application LFSR Operation rule Summary, can get the actual mode 2 operation of a circuit diagram, specific implementation please refer to Figure 7.9 Figure 7.9

Reproduced Principle of CRC32 encryption algorithm